/*
 * Copyright (c) [2020], MediaTek Inc. All rights reserved.
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. and/or its licensors.
 * Except as otherwise provided in the applicable licensing terms with
 * MediaTek Inc. and/or its licensors, any reproduction, modification, use or
 * disclosure of MediaTek Software, and information contained herein, in whole
 * or in part, shall be strictly prohibited.
*/
//[File]            : bn0_wf_arb_top.h
//[Revision time]   : Wed Dec 26 19:19:27 2018
//[Description]     : This file is auto generated by CODA
//[Copyright]       : Copyright (C) 2018 Mediatek Incorportion. All rights reserved.

#ifndef __BN0_WF_ARB_TOP_REGS_H__
#define __BN0_WF_ARB_TOP_REGS_H__

#include "hal_common.h"

#ifdef __cplusplus
extern "C" {
#endif


//****************************************************************************
//
//                     BN0_WF_ARB_TOP CR Definitions                     
//
//****************************************************************************

#define BN0_WF_ARB_TOP_BASE                                    0x820E3000

#define BN0_WF_ARB_TOP_TQSN_ADDR                               (BN0_WF_ARB_TOP_BASE + 0x000) // 3000
#define BN0_WF_ARB_TOP_TQFN_ADDR                               (BN0_WF_ARB_TOP_BASE + 0x004) // 3004
#define BN0_WF_ARB_TOP_GTNR_ADDR                               (BN0_WF_ARB_TOP_BASE + 0x008) // 3008
#define BN0_WF_ARB_TOP_WMMMUAC00_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x00C) // 300C
#define BN0_WF_ARB_TOP_WMMNAF_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x010) // 3010
#define BN0_WF_ARB_TOP_WMMNBCN_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x014) // 3014
#define BN0_WF_ARB_TOP_WMMMUAC01_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x018) // 3018
#define BN0_WF_ARB_TOP_WMMMUAC02_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x01C) // 301C
#define BN0_WF_ARB_TOP_ACQTXDOCS_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x020) // 3020
#define BN0_WF_ARB_TOP_WMMMUAC03_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x024) // 3024
#define BN0_WF_ARB_TOP_WMMMUAC10_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x028) // 3028
#define BN0_WF_ARB_TOP_WMMMUAC11_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x02C) // 302C
#define BN0_WF_ARB_TOP_TQSAXM0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x030) // 3030
#define BN0_WF_ARB_TOP_TQSTWT0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x038) // 3038
#define BN0_WF_ARB_TOP_BFSCR_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x040) // 3040
#define BN0_WF_ARB_TOP_BFSR_ADDR                               (BN0_WF_ARB_TOP_BASE + 0x044) // 3044
#define BN0_WF_ARB_TOP_BFCR2_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x048) // 3048
#define BN0_WF_ARB_TOP_WMMMUAC12_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x04C) // 304C
#define BN0_WF_ARB_TOP_WMMTF0_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x050) // 3050
#define BN0_WF_ARB_TOP_WMMTWTDL0_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x054) // 3054
#define BN0_WF_ARB_TOP_WMMTWTUL0_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x058) // 3058
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_ADDR                       (BN0_WF_ARB_TOP_BASE + 0x05C) // 305C
#define BN0_WF_ARB_TOP_DCR_ADDR                                (BN0_WF_ARB_TOP_BASE + 0x060) // 3060
#define BN0_WF_ARB_TOP_WMMMUAC13_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x064) // 3064
#define BN0_WF_ARB_TOP_WMMMUAC20_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x068) // 3068
#define BN0_WF_ARB_TOP_WMMMUAC21_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x06C) // 306C
#define BN0_WF_ARB_TOP_RQCR_ADDR                               (BN0_WF_ARB_TOP_BASE + 0x070) // 3070
#define BN0_WF_ARB_TOP_WMMMUAC22_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x074) // 3074
#define BN0_WF_ARB_TOP_WMMMUAC23_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x078) // 3078
#define BN0_WF_ARB_TOP_WMMMUAC30_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x07C) // 307C
#define BN0_WF_ARB_TOP_SCR_ADDR                                (BN0_WF_ARB_TOP_BASE + 0x080) // 3080
#define BN0_WF_ARB_TOP_WMMMUAC31_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x084) // 3084
#define BN0_WF_ARB_TOP_WMMMUAC32_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x088) // 3088
#define BN0_WF_ARB_TOP_WMMMUAC33_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x08C) // 308C
#define BN0_WF_ARB_TOP_SPTO0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x0A0) // 30A0
#define BN0_WF_ARB_TOP_SPTO1_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x0A4) // 30A4
#define BN0_WF_ARB_TOP_SPTO2_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x0A8) // 30A8
#define BN0_WF_ARB_TOP_SPTO3_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x0AC) // 30AC
#define BN0_WF_ARB_TOP_SPTOW_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x0B0) // 30B0
#define BN0_WF_ARB_TOP_BMCCR6_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x0B4) // 30B4
#define BN0_WF_ARB_TOP_TXHANGTO_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x0B8) // 30B8
#define BN0_WF_ARB_TOP_TQFAXM0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x0C0) // 30C0
#define BN0_WF_ARB_TOP_TQFTWT0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x0C8) // 30C8
#define BN0_WF_ARB_TOP_TQPAXM0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x0D0) // 30D0
#define BN0_WF_ARB_TOP_TQPTWT0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x0D8) // 30D8
#define BN0_WF_ARB_TOP_GTQR6_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x0E0) // 30E0
#define BN0_WF_ARB_TOP_GTQR8_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x0E8) // 30E8
#define BN0_WF_ARB_TOP_RSVD0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x0F0) // 30F0
#define BN0_WF_ARB_TOP_RSVD1_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x0F4) // 30F4
#define BN0_WF_ARB_TOP_RSVD_ADDR                               (BN0_WF_ARB_TOP_BASE + 0x0FC) // 30FC
#define BN0_WF_ARB_TOP_TQSW0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x100) // 3100
#define BN0_WF_ARB_TOP_TQSW1_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x104) // 3104
#define BN0_WF_ARB_TOP_TQSW2_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x108) // 3108
#define BN0_WF_ARB_TOP_TQSW3_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x10C) // 310C
#define BN0_WF_ARB_TOP_TQSM0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x110) // 3110
#define BN0_WF_ARB_TOP_TQSE0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x118) // 3118
#define BN0_WF_ARB_TOP_TQFW0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x120) // 3120
#define BN0_WF_ARB_TOP_TQFW1_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x124) // 3124
#define BN0_WF_ARB_TOP_TQFW2_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x128) // 3128
#define BN0_WF_ARB_TOP_TQFW3_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x12C) // 312C
#define BN0_WF_ARB_TOP_TQFM0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x130) // 3130
#define BN0_WF_ARB_TOP_TQFE0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x138) // 3138
#define BN0_WF_ARB_TOP_TQPW0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x140) // 3140
#define BN0_WF_ARB_TOP_TQPW1_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x144) // 3144
#define BN0_WF_ARB_TOP_TQPW2_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x148) // 3148
#define BN0_WF_ARB_TOP_TQPW3_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x14C) // 314C
#define BN0_WF_ARB_TOP_TQPM0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x150) // 3150
#define BN0_WF_ARB_TOP_BTIMCR0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x158) // 3158
#define BN0_WF_ARB_TOP_BTIMCR1_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x15C) // 315C
#define BN0_WF_ARB_TOP_BMCCR0_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x160) // 3160
#define BN0_WF_ARB_TOP_BMCCR1_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x164) // 3164
#define BN0_WF_ARB_TOP_BMCCR2_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x168) // 3168
#define BN0_WF_ARB_TOP_BMCCR3_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x16C) // 316C
#define BN0_WF_ARB_TOP_BMCCR4_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x170) // 3170
#define BN0_WF_ARB_TOP_BMCCR5_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x174) // 3174
#define BN0_WF_ARB_TOP_GTQR0_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x178) // 3178
#define BN0_WF_ARB_TOP_GTQR1_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x17C) // 317C
#define BN0_WF_ARB_TOP_GTQR2_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x180) // 3180
#define BN0_WF_ARB_TOP_GTQR3_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x184) // 3184
#define BN0_WF_ARB_TOP_GTQR4_ADDR                              (BN0_WF_ARB_TOP_BASE + 0x188) // 3188
#define BN0_WF_ARB_TOP_BFCR_ADDR                               (BN0_WF_ARB_TOP_BASE + 0x190) // 3190
#define BN0_WF_ARB_TOP_DRNGR0_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x194) // 3194
#define BN0_WF_ARB_TOP_DRNGR1_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x198) // 3198
#define BN0_WF_ARB_TOP_TXENTRYR_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x19C) // 319C
#define BN0_WF_ARB_TOP_WMMAC00_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1A0) // 31A0
#define BN0_WF_ARB_TOP_WMMAC01_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1A4) // 31A4
#define BN0_WF_ARB_TOP_WMMAC02_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1A8) // 31A8
#define BN0_WF_ARB_TOP_WMMAC03_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1AC) // 31AC
#define BN0_WF_ARB_TOP_WMMAC10_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1B0) // 31B0
#define BN0_WF_ARB_TOP_WMMAC11_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1B4) // 31B4
#define BN0_WF_ARB_TOP_WMMAC12_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1B8) // 31B8
#define BN0_WF_ARB_TOP_WMMAC13_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1BC) // 31BC
#define BN0_WF_ARB_TOP_WMMAC20_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1C0) // 31C0
#define BN0_WF_ARB_TOP_WMMAC21_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1C4) // 31C4
#define BN0_WF_ARB_TOP_WMMAC22_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1C8) // 31C8
#define BN0_WF_ARB_TOP_WMMAC23_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1CC) // 31CC
#define BN0_WF_ARB_TOP_WMMAC30_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1D0) // 31D0
#define BN0_WF_ARB_TOP_WMMAC31_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1D4) // 31D4
#define BN0_WF_ARB_TOP_WMMAC32_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1D8) // 31D8
#define BN0_WF_ARB_TOP_WMMAC33_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1DC) // 31DC
#define BN0_WF_ARB_TOP_WMMALTX0_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x1E0) // 31E0
#define BN0_WF_ARB_TOP_WMMBMC0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1E4) // 31E4
#define BN0_WF_ARB_TOP_WMMBCN0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x1E8) // 31E8
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_ADDR                      (BN0_WF_ARB_TOP_BASE + 0x1EC) // 31EC
#define BN0_WF_ARB_TOP_D0WPTAR_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x200) // 3200
#define BN0_WF_ARB_TOP_D0PTR0_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x204) // 3204
#define BN0_WF_ARB_TOP_D0PTR1_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x208) // 3208
#define BN0_WF_ARB_TOP_D0PTR2_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x20C) // 320C
#define BN0_WF_ARB_TOP_D0PTR3_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x210) // 3210
#define BN0_WF_ARB_TOP_D0PTR4_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x214) // 3214
#define BN0_WF_ARB_TOP_D0PTR5_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x218) // 3218
#define BN0_WF_ARB_TOP_D0PTWR_ADDR                             (BN0_WF_ARB_TOP_BASE + 0x21C) // 321C
#define BN0_WF_ARB_TOP_D0RWPTCR0_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x220) // 3220
#define BN0_WF_ARB_TOP_D0RWPTCR1_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x224) // 3224
#define BN0_WF_ARB_TOP_D0RWPTCR2_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x228) // 3228
#define BN0_WF_ARB_TOP_D0RWPTCR3_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x22C) // 322C
#define BN0_WF_ARB_TOP_D0RWPCR_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x230) // 3230
#define BN0_WF_ARB_TOP_D0RWPCFR0_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x234) // 3234
#define BN0_WF_ARB_TOP_D0RWPCFR1_ADDR                          (BN0_WF_ARB_TOP_BASE + 0x238) // 3238
#define BN0_WF_ARB_TOP_D0RPTDD0_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x23C) // 323C
#define BN0_WF_ARB_TOP_D0RPTDD1_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x240) // 3240
#define BN0_WF_ARB_TOP_D0RPTDD2_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x244) // 3244
#define BN0_WF_ARB_TOP_D0RPTDD3_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x248) // 3248
#define BN0_WF_ARB_TOP_D0SXCR0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x24C) // 324C
#define BN0_WF_ARB_TOP_D0SXCR1_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x250) // 3250
#define BN0_WF_ARB_TOP_D0SXCR2_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x254) // 3254
#define BN0_WF_ARB_TOP_D0PB1WERWR_ADDR                         (BN0_WF_ARB_TOP_BASE + 0x258) // 3258
#define BN0_WF_ARB_TOP_D0PTMR0_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x25C) // 325C
#define BN0_WF_ARB_TOP_D0PTMR1_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x260) // 3260
#define BN0_WF_ARB_TOP_D0PTMR2_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x264) // 3264
#define BN0_WF_ARB_TOP_D0RPTDD4_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x268) // 3268
#define BN0_WF_ARB_TOP_D0PTMR4_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x26C) // 326C
#define BN0_WF_ARB_TOP_D0PTMR5_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x270) // 3270
#define BN0_WF_ARB_TOP_D0RPTDD5_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x274) // 3274
#define BN0_WF_ARB_TOP_D0PTMR7_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x278) // 3278
#define BN0_WF_ARB_TOP_D0PTMR8_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x27C) // 327C
#define BN0_WF_ARB_TOP_D0PTMR9_ADDR                            (BN0_WF_ARB_TOP_BASE + 0x280) // 3280
#define BN0_WF_ARB_TOP_D0PTMR10_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x284) // 3284
#define BN0_WF_ARB_TOP_D0PTMR11_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x288) // 3288
#define BN0_WF_ARB_TOP_D0PTMR12_ADDR                           (BN0_WF_ARB_TOP_BASE + 0x28C) // 328C




/* =====================================================================================

  ---TQSN (0x820E3000 + 0x000)---

    NAF_START0[0]                - (W1S) Same as AC00_START0~4
    NAF_START1[1]                - (W1S) Same as AC00_START0~4
    NAF_START2[2]                - (W1S) Same as AC00_START0~4
    NAF_START3[3]                - (W1S) Same as AC00_START0~4
    RESERVED4[7..4]              - (RO) Reserved bits
    NBCN_START0[8]               - (W1S) Same as AC00_START0~4
    NBCN_START1[9]               - (W1S) Same as AC00_START0~4
    NBCN_START2[10]              - (W1S) Same as AC00_START0~4
    NBCN_START3[11]              - (W1S) Same as AC00_START0~4
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQSN_NBCN_START3_ADDR                   BN0_WF_ARB_TOP_TQSN_ADDR
#define BN0_WF_ARB_TOP_TQSN_NBCN_START3_MASK                   0x00000800                // NBCN_START3[11]
#define BN0_WF_ARB_TOP_TQSN_NBCN_START3_SHFT                   11
#define BN0_WF_ARB_TOP_TQSN_NBCN_START2_ADDR                   BN0_WF_ARB_TOP_TQSN_ADDR
#define BN0_WF_ARB_TOP_TQSN_NBCN_START2_MASK                   0x00000400                // NBCN_START2[10]
#define BN0_WF_ARB_TOP_TQSN_NBCN_START2_SHFT                   10
#define BN0_WF_ARB_TOP_TQSN_NBCN_START1_ADDR                   BN0_WF_ARB_TOP_TQSN_ADDR
#define BN0_WF_ARB_TOP_TQSN_NBCN_START1_MASK                   0x00000200                // NBCN_START1[9]
#define BN0_WF_ARB_TOP_TQSN_NBCN_START1_SHFT                   9
#define BN0_WF_ARB_TOP_TQSN_NBCN_START0_ADDR                   BN0_WF_ARB_TOP_TQSN_ADDR
#define BN0_WF_ARB_TOP_TQSN_NBCN_START0_MASK                   0x00000100                // NBCN_START0[8]
#define BN0_WF_ARB_TOP_TQSN_NBCN_START0_SHFT                   8
#define BN0_WF_ARB_TOP_TQSN_NAF_START3_ADDR                    BN0_WF_ARB_TOP_TQSN_ADDR
#define BN0_WF_ARB_TOP_TQSN_NAF_START3_MASK                    0x00000008                // NAF_START3[3]
#define BN0_WF_ARB_TOP_TQSN_NAF_START3_SHFT                    3
#define BN0_WF_ARB_TOP_TQSN_NAF_START2_ADDR                    BN0_WF_ARB_TOP_TQSN_ADDR
#define BN0_WF_ARB_TOP_TQSN_NAF_START2_MASK                    0x00000004                // NAF_START2[2]
#define BN0_WF_ARB_TOP_TQSN_NAF_START2_SHFT                    2
#define BN0_WF_ARB_TOP_TQSN_NAF_START1_ADDR                    BN0_WF_ARB_TOP_TQSN_ADDR
#define BN0_WF_ARB_TOP_TQSN_NAF_START1_MASK                    0x00000002                // NAF_START1[1]
#define BN0_WF_ARB_TOP_TQSN_NAF_START1_SHFT                    1
#define BN0_WF_ARB_TOP_TQSN_NAF_START0_ADDR                    BN0_WF_ARB_TOP_TQSN_ADDR
#define BN0_WF_ARB_TOP_TQSN_NAF_START0_MASK                    0x00000001                // NAF_START0[0]
#define BN0_WF_ARB_TOP_TQSN_NAF_START0_SHFT                    0

/* =====================================================================================

  ---TQFN (0x820E3000 + 0x004)---

    NAF_FLUSH0[0]                - (W1S) Same as AC00_FLUSH0~4
    NAF_FLUSH1[1]                - (W1S) Same as AC00_FLUSH0~4
    NAF_FLUSH2[2]                - (W1S) Same as AC00_FLUSH0~4
    NAF_FLUSH3[3]                - (W1S) Same as AC00_FLUSH0~4
    RESERVED4[7..4]              - (RO) Reserved bits
    NBCN_FLUSH0[8]               - (W1S) Same as AC00_FLUSH0~4
    NBCN_FLUSH1[9]               - (W1S) Same as AC00_FLUSH0~4
    NBCN_FLUSH2[10]              - (W1S) Same as AC00_FLUSH0~4
    NBCN_FLUSH3[11]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH3_ADDR                   BN0_WF_ARB_TOP_TQFN_ADDR
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH3_MASK                   0x00000800                // NBCN_FLUSH3[11]
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH3_SHFT                   11
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH2_ADDR                   BN0_WF_ARB_TOP_TQFN_ADDR
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH2_MASK                   0x00000400                // NBCN_FLUSH2[10]
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH2_SHFT                   10
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH1_ADDR                   BN0_WF_ARB_TOP_TQFN_ADDR
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH1_MASK                   0x00000200                // NBCN_FLUSH1[9]
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH1_SHFT                   9
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH0_ADDR                   BN0_WF_ARB_TOP_TQFN_ADDR
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH0_MASK                   0x00000100                // NBCN_FLUSH0[8]
#define BN0_WF_ARB_TOP_TQFN_NBCN_FLUSH0_SHFT                   8
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH3_ADDR                    BN0_WF_ARB_TOP_TQFN_ADDR
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH3_MASK                    0x00000008                // NAF_FLUSH3[3]
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH3_SHFT                    3
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH2_ADDR                    BN0_WF_ARB_TOP_TQFN_ADDR
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH2_MASK                    0x00000004                // NAF_FLUSH2[2]
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH2_SHFT                    2
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH1_ADDR                    BN0_WF_ARB_TOP_TQFN_ADDR
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH1_MASK                    0x00000002                // NAF_FLUSH1[1]
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH1_SHFT                    1
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH0_ADDR                    BN0_WF_ARB_TOP_TQFN_ADDR
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH0_MASK                    0x00000001                // NAF_FLUSH0[0]
#define BN0_WF_ARB_TOP_TQFN_NAF_FLUSH0_SHFT                    0

/* =====================================================================================

  ---GTNR (0x820E3000 + 0x008)---

    GUARD_TIME_NAF[7..0]         - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_NBCN[15..8]       - (RW) The same as GUARD_TIME_AC00.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_GTNR_GUARD_TIME_NBCN_ADDR               BN0_WF_ARB_TOP_GTNR_ADDR
#define BN0_WF_ARB_TOP_GTNR_GUARD_TIME_NBCN_MASK               0x0000FF00                // GUARD_TIME_NBCN[15..8]
#define BN0_WF_ARB_TOP_GTNR_GUARD_TIME_NBCN_SHFT               8
#define BN0_WF_ARB_TOP_GTNR_GUARD_TIME_NAF_ADDR                BN0_WF_ARB_TOP_GTNR_ADDR
#define BN0_WF_ARB_TOP_GTNR_GUARD_TIME_NAF_MASK                0x000000FF                // GUARD_TIME_NAF[7..0]
#define BN0_WF_ARB_TOP_GTNR_GUARD_TIME_NAF_SHFT                0

/* =====================================================================================

  ---WMMMUAC00 (0x820E3000 + 0x00C)---

    MUAIFS_AC00[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC00[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC00[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC00[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC00_CURR_MUCW_AC00_ADDR           BN0_WF_ARB_TOP_WMMMUAC00_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC00_CURR_MUCW_AC00_MASK           0x1F000000                // CURR_MUCW_AC00[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC00_CURR_MUCW_AC00_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC00_MUCWMAX_AC00_ADDR             BN0_WF_ARB_TOP_WMMMUAC00_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC00_MUCWMAX_AC00_MASK             0x001F0000                // MUCWMAX_AC00[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC00_MUCWMAX_AC00_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC00_MUCWMIN_AC00_ADDR             BN0_WF_ARB_TOP_WMMMUAC00_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC00_MUCWMIN_AC00_MASK             0x00001F00                // MUCWMIN_AC00[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC00_MUCWMIN_AC00_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC00_MUAIFS_AC00_ADDR              BN0_WF_ARB_TOP_WMMMUAC00_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC00_MUAIFS_AC00_MASK              0x0000000F                // MUAIFS_AC00[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC00_MUAIFS_AC00_SHFT              0

/* =====================================================================================

  ---WMMNAF (0x820E3000 + 0x010)---

    AIFS_NAF[3..0]               - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWT2_NAF[12..8]              - (RW) The T2 contention window in unit of slot for NAF. The value shall be set to (2^n - 1).
                                      0: means CW T2 is 16'b0000_0000_0000_0000
                                      1: means CW T2 is 16'b0000_0000_0000_0001
                                      2: means CW T2 is 16'b0000_0000_0000_0011
                                      ...
                                      n: means CW T2 is (2^n - 1)
                                      ...
                                     16: means CW T2 is 16'b1111_1111_1111_1111
                                     17~31: reserved
    RESERVED13[15..13]           - (RO) Reserved bits
    CWT3_NAF[20..16]             - (RW) The T3 contention window in unit of slot for NAF. The value shall be set to (2^n - 1).
                                      0: means CW T3 is 16'b0000_0000_0000_0000
                                      1: means CW T3 is 16'b0000_0000_0000_0001
                                      2: means CW T3 is 16'b0000_0000_0000_0011
                                      ...
                                      n: means CW T3 is (2^n - 1)
                                      ...
                                     16: means CW T3 is 16'b1111_1111_1111_1111
                                     17~31: reserved
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_NAF[28..24]          - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMNAF_CURR_CW_NAF_ADDR                 BN0_WF_ARB_TOP_WMMNAF_ADDR
#define BN0_WF_ARB_TOP_WMMNAF_CURR_CW_NAF_MASK                 0x1F000000                // CURR_CW_NAF[28..24]
#define BN0_WF_ARB_TOP_WMMNAF_CURR_CW_NAF_SHFT                 24
#define BN0_WF_ARB_TOP_WMMNAF_CWT3_NAF_ADDR                    BN0_WF_ARB_TOP_WMMNAF_ADDR
#define BN0_WF_ARB_TOP_WMMNAF_CWT3_NAF_MASK                    0x001F0000                // CWT3_NAF[20..16]
#define BN0_WF_ARB_TOP_WMMNAF_CWT3_NAF_SHFT                    16
#define BN0_WF_ARB_TOP_WMMNAF_CWT2_NAF_ADDR                    BN0_WF_ARB_TOP_WMMNAF_ADDR
#define BN0_WF_ARB_TOP_WMMNAF_CWT2_NAF_MASK                    0x00001F00                // CWT2_NAF[12..8]
#define BN0_WF_ARB_TOP_WMMNAF_CWT2_NAF_SHFT                    8
#define BN0_WF_ARB_TOP_WMMNAF_AIFS_NAF_ADDR                    BN0_WF_ARB_TOP_WMMNAF_ADDR
#define BN0_WF_ARB_TOP_WMMNAF_AIFS_NAF_MASK                    0x0000000F                // AIFS_NAF[3..0]
#define BN0_WF_ARB_TOP_WMMNAF_AIFS_NAF_SHFT                    0

/* =====================================================================================

  ---WMMNBCN (0x820E3000 + 0x014)---

    AIFS_NBCN[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_NBCN[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMNBCN_CWMIN_NBCN_ADDR                 BN0_WF_ARB_TOP_WMMNBCN_ADDR
#define BN0_WF_ARB_TOP_WMMNBCN_CWMIN_NBCN_MASK                 0x00001F00                // CWMIN_NBCN[12..8]
#define BN0_WF_ARB_TOP_WMMNBCN_CWMIN_NBCN_SHFT                 8
#define BN0_WF_ARB_TOP_WMMNBCN_AIFS_NBCN_ADDR                  BN0_WF_ARB_TOP_WMMNBCN_ADDR
#define BN0_WF_ARB_TOP_WMMNBCN_AIFS_NBCN_MASK                  0x0000000F                // AIFS_NBCN[3..0]
#define BN0_WF_ARB_TOP_WMMNBCN_AIFS_NBCN_SHFT                  0

/* =====================================================================================

  ---WMMMUAC01 (0x820E3000 + 0x018)---

    MUAIFS_AC01[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC01[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC01[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC01[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC01_CURR_MUCW_AC01_ADDR           BN0_WF_ARB_TOP_WMMMUAC01_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC01_CURR_MUCW_AC01_MASK           0x1F000000                // CURR_MUCW_AC01[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC01_CURR_MUCW_AC01_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC01_MUCWMAX_AC01_ADDR             BN0_WF_ARB_TOP_WMMMUAC01_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC01_MUCWMAX_AC01_MASK             0x001F0000                // MUCWMAX_AC01[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC01_MUCWMAX_AC01_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC01_MUCWMIN_AC01_ADDR             BN0_WF_ARB_TOP_WMMMUAC01_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC01_MUCWMIN_AC01_MASK             0x00001F00                // MUCWMIN_AC01[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC01_MUCWMIN_AC01_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC01_MUAIFS_AC01_ADDR              BN0_WF_ARB_TOP_WMMMUAC01_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC01_MUAIFS_AC01_MASK              0x0000000F                // MUAIFS_AC01[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC01_MUAIFS_AC01_SHFT              0

/* =====================================================================================

  ---WMMMUAC02 (0x820E3000 + 0x01C)---

    MUAIFS_AC02[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC02[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC02[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC02[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC02_CURR_MUCW_AC02_ADDR           BN0_WF_ARB_TOP_WMMMUAC02_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC02_CURR_MUCW_AC02_MASK           0x1F000000                // CURR_MUCW_AC02[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC02_CURR_MUCW_AC02_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC02_MUCWMAX_AC02_ADDR             BN0_WF_ARB_TOP_WMMMUAC02_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC02_MUCWMAX_AC02_MASK             0x001F0000                // MUCWMAX_AC02[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC02_MUCWMAX_AC02_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC02_MUCWMIN_AC02_ADDR             BN0_WF_ARB_TOP_WMMMUAC02_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC02_MUCWMIN_AC02_MASK             0x00001F00                // MUCWMIN_AC02[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC02_MUCWMIN_AC02_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC02_MUAIFS_AC02_ADDR              BN0_WF_ARB_TOP_WMMMUAC02_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC02_MUAIFS_AC02_MASK              0x0000000F                // MUAIFS_AC02[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC02_MUAIFS_AC02_SHFT              0

/* =====================================================================================

  ---ACQTXDOCS (0x820E3000 + 0x020)---

    AC00_TXDOTXC_SEL[0]          - (RW) 0: Select TxD AC00
                                     1: Select TxC AC00
    AC01_TXDOTXC_SEL[1]          - (RW) 0: Select TxD AC01
                                     1: Select TxC AC01
    AC02_TXDOTXC_SEL[2]          - (RW) 0: Select TxD AC02
                                     1: Select TxC AC02
    AC03_TXDOTXC_SEL[3]          - (RW) 0: Select TxD AC03
                                     1: Select TxC AC03
    AC10_TXDOTXC_SEL[4]          - (RW) 0: Select TxD AC10
                                     1: Select TxC AC10
    AC11_TXDOTXC_SEL[5]          - (RW) 0: Select TxD AC11
                                     1: Select TxC AC11
    AC12_TXDOTXC_SEL[6]          - (RW) 0: Select TxD AC12
                                     1: Select TxC AC12
    AC13_TXDOTXC_SEL[7]          - (RW) 0: Select TxD AC13
                                     1: Select TxC AC13
    AC20_TXDOTXC_SEL[8]          - (RW) 0: Select TxD AC20
                                     1: Select TxC AC20
    AC21_TXDOTXC_SEL[9]          - (RW) 0: Select TxD AC21
                                     1: Select TxC AC21
    AC22_TXDOTXC_SEL[10]         - (RW) 0: Select TxD AC22
                                     1: Select TxC AC22
    AC23_TXDOTXC_SEL[11]         - (RW) 0: Select TxD AC23
                                     1: Select TxC AC23
    AC30_TXDOTXC_SEL[12]         - (RW) 0: Select TxD AC30
                                     1: Select TxC AC30
    AC31_TXDOTXC_SEL[13]         - (RW) 0: Select TxD AC31
                                     1: Select TxC AC31
    AC32_TXDOTXC_SEL[14]         - (RW) 0: Select TxD AC32
                                     1: Select TxC AC32
    AC33_TXDOTXC_SEL[15]         - (RW) 0: Select TxD AC33
                                     1: Select TxC AC33
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC33_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC33_TXDOTXC_SEL_MASK         0x00008000                // AC33_TXDOTXC_SEL[15]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC33_TXDOTXC_SEL_SHFT         15
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC32_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC32_TXDOTXC_SEL_MASK         0x00004000                // AC32_TXDOTXC_SEL[14]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC32_TXDOTXC_SEL_SHFT         14
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC31_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC31_TXDOTXC_SEL_MASK         0x00002000                // AC31_TXDOTXC_SEL[13]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC31_TXDOTXC_SEL_SHFT         13
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC30_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC30_TXDOTXC_SEL_MASK         0x00001000                // AC30_TXDOTXC_SEL[12]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC30_TXDOTXC_SEL_SHFT         12
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC23_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC23_TXDOTXC_SEL_MASK         0x00000800                // AC23_TXDOTXC_SEL[11]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC23_TXDOTXC_SEL_SHFT         11
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC22_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC22_TXDOTXC_SEL_MASK         0x00000400                // AC22_TXDOTXC_SEL[10]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC22_TXDOTXC_SEL_SHFT         10
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC21_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC21_TXDOTXC_SEL_MASK         0x00000200                // AC21_TXDOTXC_SEL[9]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC21_TXDOTXC_SEL_SHFT         9
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC20_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC20_TXDOTXC_SEL_MASK         0x00000100                // AC20_TXDOTXC_SEL[8]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC20_TXDOTXC_SEL_SHFT         8
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC13_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC13_TXDOTXC_SEL_MASK         0x00000080                // AC13_TXDOTXC_SEL[7]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC13_TXDOTXC_SEL_SHFT         7
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC12_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC12_TXDOTXC_SEL_MASK         0x00000040                // AC12_TXDOTXC_SEL[6]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC12_TXDOTXC_SEL_SHFT         6
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC11_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC11_TXDOTXC_SEL_MASK         0x00000020                // AC11_TXDOTXC_SEL[5]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC11_TXDOTXC_SEL_SHFT         5
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC10_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC10_TXDOTXC_SEL_MASK         0x00000010                // AC10_TXDOTXC_SEL[4]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC10_TXDOTXC_SEL_SHFT         4
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC03_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC03_TXDOTXC_SEL_MASK         0x00000008                // AC03_TXDOTXC_SEL[3]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC03_TXDOTXC_SEL_SHFT         3
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC02_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC02_TXDOTXC_SEL_MASK         0x00000004                // AC02_TXDOTXC_SEL[2]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC02_TXDOTXC_SEL_SHFT         2
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC01_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC01_TXDOTXC_SEL_MASK         0x00000002                // AC01_TXDOTXC_SEL[1]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC01_TXDOTXC_SEL_SHFT         1
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC00_TXDOTXC_SEL_ADDR         BN0_WF_ARB_TOP_ACQTXDOCS_ADDR
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC00_TXDOTXC_SEL_MASK         0x00000001                // AC00_TXDOTXC_SEL[0]
#define BN0_WF_ARB_TOP_ACQTXDOCS_AC00_TXDOTXC_SEL_SHFT         0

/* =====================================================================================

  ---WMMMUAC03 (0x820E3000 + 0x024)---

    MUAIFS_AC03[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC03[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC03[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC03[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC03_CURR_MUCW_AC03_ADDR           BN0_WF_ARB_TOP_WMMMUAC03_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC03_CURR_MUCW_AC03_MASK           0x1F000000                // CURR_MUCW_AC03[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC03_CURR_MUCW_AC03_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC03_MUCWMAX_AC03_ADDR             BN0_WF_ARB_TOP_WMMMUAC03_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC03_MUCWMAX_AC03_MASK             0x001F0000                // MUCWMAX_AC03[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC03_MUCWMAX_AC03_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC03_MUCWMIN_AC03_ADDR             BN0_WF_ARB_TOP_WMMMUAC03_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC03_MUCWMIN_AC03_MASK             0x00001F00                // MUCWMIN_AC03[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC03_MUCWMIN_AC03_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC03_MUAIFS_AC03_ADDR              BN0_WF_ARB_TOP_WMMMUAC03_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC03_MUAIFS_AC03_MASK              0x0000000F                // MUAIFS_AC03[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC03_MUAIFS_AC03_SHFT              0

/* =====================================================================================

  ---WMMMUAC10 (0x820E3000 + 0x028)---

    MUAIFS_AC10[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC10[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC10[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC10[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC10_CURR_MUCW_AC10_ADDR           BN0_WF_ARB_TOP_WMMMUAC10_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC10_CURR_MUCW_AC10_MASK           0x1F000000                // CURR_MUCW_AC10[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC10_CURR_MUCW_AC10_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC10_MUCWMAX_AC10_ADDR             BN0_WF_ARB_TOP_WMMMUAC10_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC10_MUCWMAX_AC10_MASK             0x001F0000                // MUCWMAX_AC10[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC10_MUCWMAX_AC10_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC10_MUCWMIN_AC10_ADDR             BN0_WF_ARB_TOP_WMMMUAC10_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC10_MUCWMIN_AC10_MASK             0x00001F00                // MUCWMIN_AC10[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC10_MUCWMIN_AC10_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC10_MUAIFS_AC10_ADDR              BN0_WF_ARB_TOP_WMMMUAC10_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC10_MUAIFS_AC10_MASK              0x0000000F                // MUAIFS_AC10[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC10_MUAIFS_AC10_SHFT              0

/* =====================================================================================

  ---WMMMUAC11 (0x820E3000 + 0x02C)---

    MUAIFS_AC11[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC11[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC11[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC11[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC11_CURR_MUCW_AC11_ADDR           BN0_WF_ARB_TOP_WMMMUAC11_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC11_CURR_MUCW_AC11_MASK           0x1F000000                // CURR_MUCW_AC11[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC11_CURR_MUCW_AC11_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC11_MUCWMAX_AC11_ADDR             BN0_WF_ARB_TOP_WMMMUAC11_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC11_MUCWMAX_AC11_MASK             0x001F0000                // MUCWMAX_AC11[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC11_MUCWMAX_AC11_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC11_MUCWMIN_AC11_ADDR             BN0_WF_ARB_TOP_WMMMUAC11_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC11_MUCWMIN_AC11_MASK             0x00001F00                // MUCWMIN_AC11[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC11_MUCWMIN_AC11_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC11_MUAIFS_AC11_ADDR              BN0_WF_ARB_TOP_WMMMUAC11_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC11_MUAIFS_AC11_MASK              0x0000000F                // MUAIFS_AC11[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC11_MUAIFS_AC11_SHFT              0

/* =====================================================================================

  ---TQSAXM0 (0x820E3000 + 0x030)---

    TXCMD_TF0_START0[0]          - (W1S) Same as AC00_START0~4
    TXCMD_TF0_START1[1]          - (W1S) Same as AC00_START0~4
    TXCMD_TF0_START2[2]          - (W1S) Same as AC00_START0~4
    TXCMD_TF0_START3[3]          - (W1S) Same as AC00_START0~4
    TXCMD_TF0_START4[4]          - (W1S) Same as AC00_START0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    TXCMD_ALTX0_START0[8]        - (W1S) Same as AC00_START0~4
    TXCMD_ALTX0_START1[9]        - (W1S) Same as AC00_START0~4
    TXCMD_ALTX0_START2[10]       - (W1S) Same as AC00_START0~4
    TXCMD_ALTX0_START3[11]       - (W1S) Same as AC00_START0~4
    TXCMD_ALTX0_START4[12]       - (W1S) Same as AC00_START0~4
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START4_ADDR         BN0_WF_ARB_TOP_TQSAXM0_ADDR
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START4_MASK         0x00001000                // TXCMD_ALTX0_START4[12]
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START4_SHFT         12
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START3_ADDR         BN0_WF_ARB_TOP_TQSAXM0_ADDR
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START3_MASK         0x00000800                // TXCMD_ALTX0_START3[11]
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START3_SHFT         11
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START2_ADDR         BN0_WF_ARB_TOP_TQSAXM0_ADDR
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START2_MASK         0x00000400                // TXCMD_ALTX0_START2[10]
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START2_SHFT         10
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START1_ADDR         BN0_WF_ARB_TOP_TQSAXM0_ADDR
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START1_MASK         0x00000200                // TXCMD_ALTX0_START1[9]
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START1_SHFT         9
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START0_ADDR         BN0_WF_ARB_TOP_TQSAXM0_ADDR
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START0_MASK         0x00000100                // TXCMD_ALTX0_START0[8]
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_ALTX0_START0_SHFT         8
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START4_ADDR           BN0_WF_ARB_TOP_TQSAXM0_ADDR
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START4_MASK           0x00000010                // TXCMD_TF0_START4[4]
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START4_SHFT           4
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START3_ADDR           BN0_WF_ARB_TOP_TQSAXM0_ADDR
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START3_MASK           0x00000008                // TXCMD_TF0_START3[3]
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START3_SHFT           3
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START2_ADDR           BN0_WF_ARB_TOP_TQSAXM0_ADDR
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START2_MASK           0x00000004                // TXCMD_TF0_START2[2]
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START2_SHFT           2
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START1_ADDR           BN0_WF_ARB_TOP_TQSAXM0_ADDR
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START1_MASK           0x00000002                // TXCMD_TF0_START1[1]
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START1_SHFT           1
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START0_ADDR           BN0_WF_ARB_TOP_TQSAXM0_ADDR
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START0_MASK           0x00000001                // TXCMD_TF0_START0[0]
#define BN0_WF_ARB_TOP_TQSAXM0_TXCMD_TF0_START0_SHFT           0

/* =====================================================================================

  ---TQSTWT0 (0x820E3000 + 0x038)---

    TXCMD_TWT_DL0_START0[0]      - (W1S) Same as AC00_START0~4
    TXCMD_TWT_DL0_START1[1]      - (W1S) Same as AC00_START0~4
    TXCMD_TWT_DL0_START2[2]      - (W1S) Same as AC00_START0~4
    TXCMD_TWT_DL0_START3[3]      - (W1S) Same as AC00_START0~4
    TXCMD_TWT_DL0_START4[4]      - (W1S) Same as AC00_START0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    TXCMD_TWT_UL0_START0[8]      - (W1S) Same as AC00_START0~4
    TXCMD_TWT_UL0_START1[9]      - (W1S) Same as AC00_START0~4
    TXCMD_TWT_UL0_START2[10]     - (W1S) Same as AC00_START0~4
    TXCMD_TWT_UL0_START3[11]     - (W1S) Same as AC00_START0~4
    TXCMD_TWT_UL0_START4[12]     - (W1S) Same as AC00_START0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    TXCMD_TWT_TSF_TF0_START0[16] - (W1S) Same as AC00_START0~4
    TXCMD_TWT_TSF_TF0_START1[17] - (W1S) Same as AC00_START0~4
    TXCMD_TWT_TSF_TF0_START2[18] - (W1S) Same as AC00_START0~4
    TXCMD_TWT_TSF_TF0_START3[19] - (W1S) Same as AC00_START0~4
    TXCMD_TWT_TSF_TF0_START4[20] - (W1S) Same as AC00_START0~4
    RESERVED21[31..21]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START4_ADDR   BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START4_MASK   0x00100000                // TXCMD_TWT_TSF_TF0_START4[20]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START4_SHFT   20
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START3_ADDR   BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START3_MASK   0x00080000                // TXCMD_TWT_TSF_TF0_START3[19]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START3_SHFT   19
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START2_ADDR   BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START2_MASK   0x00040000                // TXCMD_TWT_TSF_TF0_START2[18]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START2_SHFT   18
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START1_ADDR   BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START1_MASK   0x00020000                // TXCMD_TWT_TSF_TF0_START1[17]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START1_SHFT   17
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START0_ADDR   BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START0_MASK   0x00010000                // TXCMD_TWT_TSF_TF0_START0[16]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_TSF_TF0_START0_SHFT   16
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START4_ADDR       BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START4_MASK       0x00001000                // TXCMD_TWT_UL0_START4[12]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START4_SHFT       12
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START3_ADDR       BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START3_MASK       0x00000800                // TXCMD_TWT_UL0_START3[11]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START3_SHFT       11
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START2_ADDR       BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START2_MASK       0x00000400                // TXCMD_TWT_UL0_START2[10]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START2_SHFT       10
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START1_ADDR       BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START1_MASK       0x00000200                // TXCMD_TWT_UL0_START1[9]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START1_SHFT       9
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START0_ADDR       BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START0_MASK       0x00000100                // TXCMD_TWT_UL0_START0[8]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_UL0_START0_SHFT       8
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START4_ADDR       BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START4_MASK       0x00000010                // TXCMD_TWT_DL0_START4[4]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START4_SHFT       4
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START3_ADDR       BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START3_MASK       0x00000008                // TXCMD_TWT_DL0_START3[3]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START3_SHFT       3
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START2_ADDR       BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START2_MASK       0x00000004                // TXCMD_TWT_DL0_START2[2]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START2_SHFT       2
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START1_ADDR       BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START1_MASK       0x00000002                // TXCMD_TWT_DL0_START1[1]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START1_SHFT       1
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START0_ADDR       BN0_WF_ARB_TOP_TQSTWT0_ADDR
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START0_MASK       0x00000001                // TXCMD_TWT_DL0_START0[0]
#define BN0_WF_ARB_TOP_TQSTWT0_TXCMD_TWT_DL0_START0_SHFT       0

/* =====================================================================================

  ---BFSCR (0x820E3000 + 0x040)---

    BFSTS_SEL[4..0]              - (RW) Back-off status selector. It means Tx queue ID
                                      0~15: AC00~33
                                      16: ALTX0
                                      17: BMC0
                                      18: BCN0
                                      19: N/A
                                      20: ALTX1
                                      21: BMC1
                                      22: BCN1
                                      23: RWP
                                      24: NAF
                                      25: NBCN
                                      26~31: N/A
    RESERVED5[31..5]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BFSCR_BFSTS_SEL_ADDR                    BN0_WF_ARB_TOP_BFSCR_ADDR
#define BN0_WF_ARB_TOP_BFSCR_BFSTS_SEL_MASK                    0x0000001F                // BFSTS_SEL[4..0]
#define BN0_WF_ARB_TOP_BFSCR_BFSTS_SEL_SHFT                    0

/* =====================================================================================

  ---BFSR (0x820E3000 + 0x044)---

    QUE_BFN[15..0]               - (RO) The current BFN in unit of slot for this queue. The queue depend on BFSTS_SEL.
    QUE_IFS[19..16]              - (RO) The current IFS in unit of slot for this queue. The queue depend on BFSTS_SEL.
    QUE_CURR_CW[24..20]          - (RO) The current contention window in unit of slot for this queue. The queue depend on BFSTS_SEL. The value is always (2^n - 1).
                                     0: means current CW is 16'b0000_0000_0000_0000
                                      1: means current CW is 16'b0000_0000_0000_0001
                                      2: means current CW is 16'b0000_0000_0000_0011
                                      ...
                                      n: means current CW is (2^n - 1)
                                      ...
                                     16: means current CW is 16'b1111_1111_1111_1111
                                     17~31: reserved
    RESERVED25[31..25]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BFSR_QUE_CURR_CW_ADDR                   BN0_WF_ARB_TOP_BFSR_ADDR
#define BN0_WF_ARB_TOP_BFSR_QUE_CURR_CW_MASK                   0x01F00000                // QUE_CURR_CW[24..20]
#define BN0_WF_ARB_TOP_BFSR_QUE_CURR_CW_SHFT                   20
#define BN0_WF_ARB_TOP_BFSR_QUE_IFS_ADDR                       BN0_WF_ARB_TOP_BFSR_ADDR
#define BN0_WF_ARB_TOP_BFSR_QUE_IFS_MASK                       0x000F0000                // QUE_IFS[19..16]
#define BN0_WF_ARB_TOP_BFSR_QUE_IFS_SHFT                       16
#define BN0_WF_ARB_TOP_BFSR_QUE_BFN_ADDR                       BN0_WF_ARB_TOP_BFSR_ADDR
#define BN0_WF_ARB_TOP_BFSR_QUE_BFN_MASK                       0x0000FFFF                // QUE_BFN[15..0]
#define BN0_WF_ARB_TOP_BFSR_QUE_BFN_SHFT                       0

/* =====================================================================================

  ---BFCR2 (0x820E3000 + 0x048)---

    BFN_MODE0[1..0]              - (RW) This CR allows TX Hang prevention for backoff-timeout event 0.
                                     2'b00 : TX Hang prevention.
                                     2'b01 : Old behavior. Thus, NO TX Hang prevention. Such TX Hang has been found in FALCON TX boundary case at queue empty flag falling with slot idle when old behavior is chosen. Thus, old behavior should not be used. Old behavior is remained only for precaution.
                                     others : Old behavior. Thus, NO TX Hang prevention. Such TX Hang has been found in Cervino/7663 FPGA when old behavior is chosen. Thus, old behavior should not be used. Old behavior is remained only for precaution.
    BFN_MODE1[3..2]              - (RW) This CR allows TX Hang prevention for backoff-timeout event 0.
                                     2'b00 : TX Hang prevention.
                                     2'b01 : Old behavior. Thus, NO TX Hang prevention. Such TX Hang has been found in FALCON TX boundary case at queue empty flag falling with slot idle when old behavior is chosen. Thus, old behavior should not be used. Old behavior is remained only for precaution.
                                     others : Old behavior. Thus, NO TX Hang prevention. Such TX Hang has been found in Cervino/7663 FPGA when old behavior is chosen. Thus, old behavior should not be used. Old behavior is remained only for precaution.
    BFN_MODE2[5..4]              - (RW) This CR allows TX Hang prevention for backoff-timeout event 0.
                                     2'b00 : TX Hang prevention.
                                     2'b01 : Old behavior. Thus, NO TX Hang prevention. Such TX Hang has been found in FALCON TX boundary case at queue empty flag falling with slot idle when old behavior is chosen. Thus, old behavior should not be used. Old behavior is remained only for precaution.
                                     others : Old behavior. Thus, NO TX Hang prevention. Such TX Hang has been found in Cervino/7663 FPGA when old behavior is chosen. Thus, old behavior should not be used. Old behavior is remained only for precaution.
    BFN_MODE3[7..6]              - (RW) This CR allows TX Hang prevention for backoff-timeout event 0.
                                     2'b00 : TX Hang prevention.
                                     2'b01 : Old behavior. Thus, NO TX Hang prevention. Such TX Hang has been found in FALCON TX boundary case at queue empty flag falling with slot idle when old behavior is chosen. Thus, old behavior should not be used. Old behavior is remained only for precaution.
                                     others : Old behavior. Thus, NO TX Hang prevention. Such TX Hang has been found in Cervino/7663 FPGA when old behavior is chosen. Thus, old behavior should not be used. Old behavior is remained only for precaution.
    MUEDCA_RISE_MODE[10..8]      - (RW) MUEDCA_RISE_MODE[0] : When LP_MU_EDCA_FLAG rises, the CW will be clear.
                                     1: clear to CWmin.
                                     0: continue the previous CW.
                                     MUEDCA_RISE_MODE[1] : When LP_MU_EDCA_FLAG rises, the IFS will be reload.
                                     1: reload IFS.
                                     0: Continue the previous IFS.
                                     MUEDCA_RISE_MODE[2] : When LP_MU_EDCA_FLAG rises, the BFN will be reload.
                                     1: reload BFN.
                                     0: Continue the previous BFN.
    RESERVED11[11]               - (RO) Reserved bits
    MUEDCA_FALL_MODE[14..12]     - (RW) MUEDCA_FALL_MODE[0] : When LP_MU_EDCA_FLAG falls, the CW will be clear.
                                     1: clear to CWmin.
                                     0: continue the previous CW.
                                     MUEDCA_FALL_MODE[1] : When LP_MU_EDCA_FLAG falls, the IFS will be reload.
                                     1: reload IFS.
                                     0: Continue the previous IFS.
                                     MUEDCA_FALL_MODE[2] : When LP_MU_EDCA_FLAG falls, the BFN will be reload.
                                     1: reload BFN.
                                     0: Continue the previous BFN.
    RESERVED15[15]               - (RO) Reserved bits
    NO_PREMATURE_EARLY_BF_FREEZE[16] - (RW) When early backoff timeout is enabled (for pre-load), this CR prevents all backoff engines from being frozen prematurely as AGG receives arb0/1_tx_start earlier than arb0/1_tx_active. Such avoidance will avoid TX Hang.
                                     0: Disabled.
                                     1: Enabled.
    RESERVED17[31..17]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BFCR2_NO_PREMATURE_EARLY_BF_FREEZE_ADDR BN0_WF_ARB_TOP_BFCR2_ADDR
#define BN0_WF_ARB_TOP_BFCR2_NO_PREMATURE_EARLY_BF_FREEZE_MASK 0x00010000                // NO_PREMATURE_EARLY_BF_FREEZE[16]
#define BN0_WF_ARB_TOP_BFCR2_NO_PREMATURE_EARLY_BF_FREEZE_SHFT 16
#define BN0_WF_ARB_TOP_BFCR2_MUEDCA_FALL_MODE_ADDR             BN0_WF_ARB_TOP_BFCR2_ADDR
#define BN0_WF_ARB_TOP_BFCR2_MUEDCA_FALL_MODE_MASK             0x00007000                // MUEDCA_FALL_MODE[14..12]
#define BN0_WF_ARB_TOP_BFCR2_MUEDCA_FALL_MODE_SHFT             12
#define BN0_WF_ARB_TOP_BFCR2_MUEDCA_RISE_MODE_ADDR             BN0_WF_ARB_TOP_BFCR2_ADDR
#define BN0_WF_ARB_TOP_BFCR2_MUEDCA_RISE_MODE_MASK             0x00000700                // MUEDCA_RISE_MODE[10..8]
#define BN0_WF_ARB_TOP_BFCR2_MUEDCA_RISE_MODE_SHFT             8
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE3_ADDR                    BN0_WF_ARB_TOP_BFCR2_ADDR
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE3_MASK                    0x000000C0                // BFN_MODE3[7..6]
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE3_SHFT                    6
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE2_ADDR                    BN0_WF_ARB_TOP_BFCR2_ADDR
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE2_MASK                    0x00000030                // BFN_MODE2[5..4]
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE2_SHFT                    4
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE1_ADDR                    BN0_WF_ARB_TOP_BFCR2_ADDR
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE1_MASK                    0x0000000C                // BFN_MODE1[3..2]
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE1_SHFT                    2
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE0_ADDR                    BN0_WF_ARB_TOP_BFCR2_ADDR
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE0_MASK                    0x00000003                // BFN_MODE0[1..0]
#define BN0_WF_ARB_TOP_BFCR2_BFN_MODE0_SHFT                    0

/* =====================================================================================

  ---WMMMUAC12 (0x820E3000 + 0x04C)---

    MUAIFS_AC12[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC12[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC12[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC12[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC12_CURR_MUCW_AC12_ADDR           BN0_WF_ARB_TOP_WMMMUAC12_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC12_CURR_MUCW_AC12_MASK           0x1F000000                // CURR_MUCW_AC12[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC12_CURR_MUCW_AC12_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC12_MUCWMAX_AC12_ADDR             BN0_WF_ARB_TOP_WMMMUAC12_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC12_MUCWMAX_AC12_MASK             0x001F0000                // MUCWMAX_AC12[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC12_MUCWMAX_AC12_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC12_MUCWMIN_AC12_ADDR             BN0_WF_ARB_TOP_WMMMUAC12_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC12_MUCWMIN_AC12_MASK             0x00001F00                // MUCWMIN_AC12[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC12_MUCWMIN_AC12_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC12_MUAIFS_AC12_ADDR              BN0_WF_ARB_TOP_WMMMUAC12_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC12_MUAIFS_AC12_MASK              0x0000000F                // MUAIFS_AC12[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC12_MUAIFS_AC12_SHFT              0

/* =====================================================================================

  ---WMMTF0 (0x820E3000 + 0x050)---

    AIFS_TF0[3..0]               - (RW) The same as AIFS_AC00.
    RESERVED4[6..4]              - (RO) Reserved bits
    SLOT_IDLE_TF0_SEL[7]         - (RW)  xxx 
    CWMIN_TF0[12..8]             - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_TF0[20..16]            - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_TF0[28..24]          - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMTF0_CURR_CW_TF0_ADDR                 BN0_WF_ARB_TOP_WMMTF0_ADDR
#define BN0_WF_ARB_TOP_WMMTF0_CURR_CW_TF0_MASK                 0x1F000000                // CURR_CW_TF0[28..24]
#define BN0_WF_ARB_TOP_WMMTF0_CURR_CW_TF0_SHFT                 24
#define BN0_WF_ARB_TOP_WMMTF0_CWMAX_TF0_ADDR                   BN0_WF_ARB_TOP_WMMTF0_ADDR
#define BN0_WF_ARB_TOP_WMMTF0_CWMAX_TF0_MASK                   0x001F0000                // CWMAX_TF0[20..16]
#define BN0_WF_ARB_TOP_WMMTF0_CWMAX_TF0_SHFT                   16
#define BN0_WF_ARB_TOP_WMMTF0_CWMIN_TF0_ADDR                   BN0_WF_ARB_TOP_WMMTF0_ADDR
#define BN0_WF_ARB_TOP_WMMTF0_CWMIN_TF0_MASK                   0x00001F00                // CWMIN_TF0[12..8]
#define BN0_WF_ARB_TOP_WMMTF0_CWMIN_TF0_SHFT                   8
#define BN0_WF_ARB_TOP_WMMTF0_SLOT_IDLE_TF0_SEL_ADDR           BN0_WF_ARB_TOP_WMMTF0_ADDR
#define BN0_WF_ARB_TOP_WMMTF0_SLOT_IDLE_TF0_SEL_MASK           0x00000080                // SLOT_IDLE_TF0_SEL[7]
#define BN0_WF_ARB_TOP_WMMTF0_SLOT_IDLE_TF0_SEL_SHFT           7
#define BN0_WF_ARB_TOP_WMMTF0_AIFS_TF0_ADDR                    BN0_WF_ARB_TOP_WMMTF0_ADDR
#define BN0_WF_ARB_TOP_WMMTF0_AIFS_TF0_MASK                    0x0000000F                // AIFS_TF0[3..0]
#define BN0_WF_ARB_TOP_WMMTF0_AIFS_TF0_SHFT                    0

/* =====================================================================================

  ---WMMTWTDL0 (0x820E3000 + 0x054)---

    AIFS_TWT_DL0[3..0]           - (RW) The same as AIFS_AC00.
    RESERVED4[6..4]              - (RO) Reserved bits
    SLOT_IDLE_TWT_DL0_SEL[7]     - (RW)  xxx 
    CWMIN_TWT_DL0[12..8]         - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_TWT_DL0[20..16]        - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_TWT_DL0[28..24]      - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMTWTDL0_CURR_CW_TWT_DL0_ADDR          BN0_WF_ARB_TOP_WMMTWTDL0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTDL0_CURR_CW_TWT_DL0_MASK          0x1F000000                // CURR_CW_TWT_DL0[28..24]
#define BN0_WF_ARB_TOP_WMMTWTDL0_CURR_CW_TWT_DL0_SHFT          24
#define BN0_WF_ARB_TOP_WMMTWTDL0_CWMAX_TWT_DL0_ADDR            BN0_WF_ARB_TOP_WMMTWTDL0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTDL0_CWMAX_TWT_DL0_MASK            0x001F0000                // CWMAX_TWT_DL0[20..16]
#define BN0_WF_ARB_TOP_WMMTWTDL0_CWMAX_TWT_DL0_SHFT            16
#define BN0_WF_ARB_TOP_WMMTWTDL0_CWMIN_TWT_DL0_ADDR            BN0_WF_ARB_TOP_WMMTWTDL0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTDL0_CWMIN_TWT_DL0_MASK            0x00001F00                // CWMIN_TWT_DL0[12..8]
#define BN0_WF_ARB_TOP_WMMTWTDL0_CWMIN_TWT_DL0_SHFT            8
#define BN0_WF_ARB_TOP_WMMTWTDL0_SLOT_IDLE_TWT_DL0_SEL_ADDR    BN0_WF_ARB_TOP_WMMTWTDL0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTDL0_SLOT_IDLE_TWT_DL0_SEL_MASK    0x00000080                // SLOT_IDLE_TWT_DL0_SEL[7]
#define BN0_WF_ARB_TOP_WMMTWTDL0_SLOT_IDLE_TWT_DL0_SEL_SHFT    7
#define BN0_WF_ARB_TOP_WMMTWTDL0_AIFS_TWT_DL0_ADDR             BN0_WF_ARB_TOP_WMMTWTDL0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTDL0_AIFS_TWT_DL0_MASK             0x0000000F                // AIFS_TWT_DL0[3..0]
#define BN0_WF_ARB_TOP_WMMTWTDL0_AIFS_TWT_DL0_SHFT             0

/* =====================================================================================

  ---WMMTWTUL0 (0x820E3000 + 0x058)---

    AIFS_TWT_UL0[3..0]           - (RW) The same as AIFS_AC00.
    RESERVED4[6..4]              - (RO) Reserved bits
    SLOT_IDLE_TWT_UL0_SEL[7]     - (RW)  xxx 
    CWMIN_TWT_UL0[12..8]         - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_TWT_UL0[20..16]        - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_TWT_UL0[28..24]      - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMTWTUL0_CURR_CW_TWT_UL0_ADDR          BN0_WF_ARB_TOP_WMMTWTUL0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTUL0_CURR_CW_TWT_UL0_MASK          0x1F000000                // CURR_CW_TWT_UL0[28..24]
#define BN0_WF_ARB_TOP_WMMTWTUL0_CURR_CW_TWT_UL0_SHFT          24
#define BN0_WF_ARB_TOP_WMMTWTUL0_CWMAX_TWT_UL0_ADDR            BN0_WF_ARB_TOP_WMMTWTUL0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTUL0_CWMAX_TWT_UL0_MASK            0x001F0000                // CWMAX_TWT_UL0[20..16]
#define BN0_WF_ARB_TOP_WMMTWTUL0_CWMAX_TWT_UL0_SHFT            16
#define BN0_WF_ARB_TOP_WMMTWTUL0_CWMIN_TWT_UL0_ADDR            BN0_WF_ARB_TOP_WMMTWTUL0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTUL0_CWMIN_TWT_UL0_MASK            0x00001F00                // CWMIN_TWT_UL0[12..8]
#define BN0_WF_ARB_TOP_WMMTWTUL0_CWMIN_TWT_UL0_SHFT            8
#define BN0_WF_ARB_TOP_WMMTWTUL0_SLOT_IDLE_TWT_UL0_SEL_ADDR    BN0_WF_ARB_TOP_WMMTWTUL0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTUL0_SLOT_IDLE_TWT_UL0_SEL_MASK    0x00000080                // SLOT_IDLE_TWT_UL0_SEL[7]
#define BN0_WF_ARB_TOP_WMMTWTUL0_SLOT_IDLE_TWT_UL0_SEL_SHFT    7
#define BN0_WF_ARB_TOP_WMMTWTUL0_AIFS_TWT_UL0_ADDR             BN0_WF_ARB_TOP_WMMTWTUL0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTUL0_AIFS_TWT_UL0_MASK             0x0000000F                // AIFS_TWT_UL0[3..0]
#define BN0_WF_ARB_TOP_WMMTWTUL0_AIFS_TWT_UL0_SHFT             0

/* =====================================================================================

  ---WMMTWTTSFTF0 (0x820E3000 + 0x05C)---

    AIFS_TWT_TSF_TF0[3..0]       - (RW) The same as AIFS_AC00.
    RESERVED4[6..4]              - (RO) Reserved bits
    SLOT_IDLE_TWT_TSF_TF0_SEL[7] - (RW)  xxx 
    CWMIN_TWT_TSF_TF0[12..8]     - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_TWT_TSF_TF0[20..16]    - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_TWT_TSF_TF0[28..24]  - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_CURR_CW_TWT_TSF_TF0_ADDR   BN0_WF_ARB_TOP_WMMTWTTSFTF0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_CURR_CW_TWT_TSF_TF0_MASK   0x1F000000                // CURR_CW_TWT_TSF_TF0[28..24]
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_CURR_CW_TWT_TSF_TF0_SHFT   24
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_CWMAX_TWT_TSF_TF0_ADDR     BN0_WF_ARB_TOP_WMMTWTTSFTF0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_CWMAX_TWT_TSF_TF0_MASK     0x001F0000                // CWMAX_TWT_TSF_TF0[20..16]
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_CWMAX_TWT_TSF_TF0_SHFT     16
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_CWMIN_TWT_TSF_TF0_ADDR     BN0_WF_ARB_TOP_WMMTWTTSFTF0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_CWMIN_TWT_TSF_TF0_MASK     0x00001F00                // CWMIN_TWT_TSF_TF0[12..8]
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_CWMIN_TWT_TSF_TF0_SHFT     8
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_SLOT_IDLE_TWT_TSF_TF0_SEL_ADDR BN0_WF_ARB_TOP_WMMTWTTSFTF0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_SLOT_IDLE_TWT_TSF_TF0_SEL_MASK 0x00000080                // SLOT_IDLE_TWT_TSF_TF0_SEL[7]
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_SLOT_IDLE_TWT_TSF_TF0_SEL_SHFT 7
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_AIFS_TWT_TSF_TF0_ADDR      BN0_WF_ARB_TOP_WMMTWTTSFTF0_ADDR
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_AIFS_TWT_TSF_TF0_MASK      0x0000000F                // AIFS_TWT_TSF_TF0[3..0]
#define BN0_WF_ARB_TOP_WMMTWTTSFTF0_AIFS_TWT_TSF_TF0_SHFT      0

/* =====================================================================================

  ---DCR (0x820E3000 + 0x060)---

    DBG_EXTRA_SEL0[4..0]         - (RW) Debug extra selector. This only use for flag00, 04, 08, 0C, 10, 14, 18, 1C
                                     Flag00, 04, 08, 0C, 10: means Tx queue ID
                                      0~15: AC00~33
                                      16: ALTX0
                                      17: BMC0
                                      18: BCN0
                                      19: N/A
                                      20: ALTX1
                                      21: BMC1
                                      22: BCN1
                                      23: RWP
                                      24: NAF
                                      25: NBCN
                                      26~31: N/A
                                     Flag14, 18, 1C: means BSSID
    RESERVED5[7..5]              - (RO) Reserved bits
    DBG_EXTRA_SEL1[12..8]        - (RW) Debug extra selector. This only use for flag01, 05, 09, 0D, 11, 15, 19, 1D
                                     Flag01, 05, 09, 0D, 11: means Tx queue ID
                                     Flag15, 19, 1D: means BSSID
    RESERVED13[15..13]           - (RO) Reserved bits
    DBG_EXTRA_SEL2[20..16]       - (RW) Debug extra selector. This only use for flag02, 06, 0A, 0E, 12, 16, 1A, 1E
                                     Flag02, 06, 0A, 0E, 12: means Tx queue ID
                                     Flag16, 1A, 1E: means BSSID
    RESERVED21[23..21]           - (RO) Reserved bits
    DBG_EXTRA_SEL3[28..24]       - (RW) Debug extra selector. This only use for flag03, 07, 0B, 0F, 13, 17, 1B, 1F
                                     Flag03, 07, 0B, 0F, 13: means Tx queue ID
                                     Flag17, 1B, 1F: means BSSID
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL3_ADDR                 BN0_WF_ARB_TOP_DCR_ADDR
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL3_MASK                 0x1F000000                // DBG_EXTRA_SEL3[28..24]
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL3_SHFT                 24
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL2_ADDR                 BN0_WF_ARB_TOP_DCR_ADDR
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL2_MASK                 0x001F0000                // DBG_EXTRA_SEL2[20..16]
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL2_SHFT                 16
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL1_ADDR                 BN0_WF_ARB_TOP_DCR_ADDR
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL1_MASK                 0x00001F00                // DBG_EXTRA_SEL1[12..8]
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL1_SHFT                 8
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL0_ADDR                 BN0_WF_ARB_TOP_DCR_ADDR
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL0_MASK                 0x0000001F                // DBG_EXTRA_SEL0[4..0]
#define BN0_WF_ARB_TOP_DCR_DBG_EXTRA_SEL0_SHFT                 0

/* =====================================================================================

  ---WMMMUAC13 (0x820E3000 + 0x064)---

    MUAIFS_AC13[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC13[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC13[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC13[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC13_CURR_MUCW_AC13_ADDR           BN0_WF_ARB_TOP_WMMMUAC13_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC13_CURR_MUCW_AC13_MASK           0x1F000000                // CURR_MUCW_AC13[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC13_CURR_MUCW_AC13_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC13_MUCWMAX_AC13_ADDR             BN0_WF_ARB_TOP_WMMMUAC13_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC13_MUCWMAX_AC13_MASK             0x001F0000                // MUCWMAX_AC13[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC13_MUCWMAX_AC13_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC13_MUCWMIN_AC13_ADDR             BN0_WF_ARB_TOP_WMMMUAC13_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC13_MUCWMIN_AC13_MASK             0x00001F00                // MUCWMIN_AC13[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC13_MUCWMIN_AC13_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC13_MUAIFS_AC13_ADDR              BN0_WF_ARB_TOP_WMMMUAC13_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC13_MUAIFS_AC13_MASK              0x0000000F                // MUAIFS_AC13[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC13_MUAIFS_AC13_SHFT              0

/* =====================================================================================

  ---WMMMUAC20 (0x820E3000 + 0x068)---

    MUAIFS_AC20[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC20[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC20[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC20[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC20_CURR_MUCW_AC20_ADDR           BN0_WF_ARB_TOP_WMMMUAC20_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC20_CURR_MUCW_AC20_MASK           0x1F000000                // CURR_MUCW_AC20[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC20_CURR_MUCW_AC20_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC20_MUCWMAX_AC20_ADDR             BN0_WF_ARB_TOP_WMMMUAC20_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC20_MUCWMAX_AC20_MASK             0x001F0000                // MUCWMAX_AC20[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC20_MUCWMAX_AC20_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC20_MUCWMIN_AC20_ADDR             BN0_WF_ARB_TOP_WMMMUAC20_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC20_MUCWMIN_AC20_MASK             0x00001F00                // MUCWMIN_AC20[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC20_MUCWMIN_AC20_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC20_MUAIFS_AC20_ADDR              BN0_WF_ARB_TOP_WMMMUAC20_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC20_MUAIFS_AC20_MASK              0x0000000F                // MUAIFS_AC20[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC20_MUAIFS_AC20_SHFT              0

/* =====================================================================================

  ---WMMMUAC21 (0x820E3000 + 0x06C)---

    MUAIFS_AC21[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC21[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC21[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC21[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC21_CURR_MUCW_AC21_ADDR           BN0_WF_ARB_TOP_WMMMUAC21_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC21_CURR_MUCW_AC21_MASK           0x1F000000                // CURR_MUCW_AC21[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC21_CURR_MUCW_AC21_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC21_MUCWMAX_AC21_ADDR             BN0_WF_ARB_TOP_WMMMUAC21_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC21_MUCWMAX_AC21_MASK             0x001F0000                // MUCWMAX_AC21[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC21_MUCWMAX_AC21_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC21_MUCWMIN_AC21_ADDR             BN0_WF_ARB_TOP_WMMMUAC21_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC21_MUCWMIN_AC21_MASK             0x00001F00                // MUCWMIN_AC21[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC21_MUCWMIN_AC21_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC21_MUAIFS_AC21_ADDR              BN0_WF_ARB_TOP_WMMMUAC21_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC21_MUAIFS_AC21_MASK              0x0000000F                // MUAIFS_AC21[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC21_MUAIFS_AC21_SHFT              0

/* =====================================================================================

  ---RQCR (0x820E3000 + 0x070)---

    RX0_START[0]                 - (W1S) Start the RX0 Queue to operate for DBDC0.
                                     Firmware writes 1 to enable the DMA. Write 0 is meaningless.
                                     Read returns the RX0 queue was enable or not.
                                     There are two conditions for FW to set RX_START:
                                     1. Initial state after reset (include power-on reset and logic reset)
                                     2. Re-start RX queue after RX_RESET was set.
    RESERVED1[1]                 - (RO) Reserved bits
    RX_RESET[2]                  - (W1S) Reset RX0/1 and RX0/1 Vector Queues for DBDC0/1.
                                     Write 1 to reset queue operation, and the data and Rx Vector content in the FIFO will be dropped. Write 0 is meaningless. Read will indicate the HW current status.
                                     0: Reset request has done
                                     1: Reset request is handling
                                     If a frame is receiving while this bit is asserted, then this frame will be discarded.
    RESERVED3[3]                 - (RO) Reserved bits
    RXV0_START[4]                - (W1S) Start the RX0 Vector (RXV0) Queue to operate for DBDC0. Firmware writes 1 to enable the DMA. Write 0 is meaningless.
                                     Read returns the RXV0 queue was enable or not.
                                     There are two conditions for FW to set RXV_START:
                                     1. Initial state after reset (include power-on reset and logic reset)
                                     2. Re-start RX vector queue after RX_RESET was set.
    RESERVED5[6..5]              - (RO) Reserved bits
    RXV0_R_EN[7]                 - (RW) Rx's Rx vector enable in RXV0 queue for DBDC0. Rx's Rx vector means this Rx vector is generated by our Rx packet.
                                     0: Disable
                                     1: Enable
    RXV0_T_EN[8]                 - (RW) Tx's Rx vector enable in RXV0 queue for DBDC0. Tx's Rx vector means this Rx vector is generated by ACK/BA response to our TX packet.
                                     0: Disable
                                     1: Enable
    RESERVED9[31..9]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_RQCR_RXV0_T_EN_ADDR                     BN0_WF_ARB_TOP_RQCR_ADDR
#define BN0_WF_ARB_TOP_RQCR_RXV0_T_EN_MASK                     0x00000100                // RXV0_T_EN[8]
#define BN0_WF_ARB_TOP_RQCR_RXV0_T_EN_SHFT                     8
#define BN0_WF_ARB_TOP_RQCR_RXV0_R_EN_ADDR                     BN0_WF_ARB_TOP_RQCR_ADDR
#define BN0_WF_ARB_TOP_RQCR_RXV0_R_EN_MASK                     0x00000080                // RXV0_R_EN[7]
#define BN0_WF_ARB_TOP_RQCR_RXV0_R_EN_SHFT                     7
#define BN0_WF_ARB_TOP_RQCR_RXV0_START_ADDR                    BN0_WF_ARB_TOP_RQCR_ADDR
#define BN0_WF_ARB_TOP_RQCR_RXV0_START_MASK                    0x00000010                // RXV0_START[4]
#define BN0_WF_ARB_TOP_RQCR_RXV0_START_SHFT                    4
#define BN0_WF_ARB_TOP_RQCR_RX_RESET_ADDR                      BN0_WF_ARB_TOP_RQCR_ADDR
#define BN0_WF_ARB_TOP_RQCR_RX_RESET_MASK                      0x00000004                // RX_RESET[2]
#define BN0_WF_ARB_TOP_RQCR_RX_RESET_SHFT                      2
#define BN0_WF_ARB_TOP_RQCR_RX0_START_ADDR                     BN0_WF_ARB_TOP_RQCR_ADDR
#define BN0_WF_ARB_TOP_RQCR_RX0_START_MASK                     0x00000001                // RX0_START[0]
#define BN0_WF_ARB_TOP_RQCR_RX0_START_SHFT                     0

/* =====================================================================================

  ---WMMMUAC22 (0x820E3000 + 0x074)---

    MUAIFS_AC22[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC22[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC22[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC22[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC22_CURR_MUCW_AC22_ADDR           BN0_WF_ARB_TOP_WMMMUAC22_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC22_CURR_MUCW_AC22_MASK           0x1F000000                // CURR_MUCW_AC22[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC22_CURR_MUCW_AC22_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC22_MUCWMAX_AC22_ADDR             BN0_WF_ARB_TOP_WMMMUAC22_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC22_MUCWMAX_AC22_MASK             0x001F0000                // MUCWMAX_AC22[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC22_MUCWMAX_AC22_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC22_MUCWMIN_AC22_ADDR             BN0_WF_ARB_TOP_WMMMUAC22_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC22_MUCWMIN_AC22_MASK             0x00001F00                // MUCWMIN_AC22[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC22_MUCWMIN_AC22_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC22_MUAIFS_AC22_ADDR              BN0_WF_ARB_TOP_WMMMUAC22_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC22_MUAIFS_AC22_MASK              0x0000000F                // MUAIFS_AC22[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC22_MUAIFS_AC22_SHFT              0

/* =====================================================================================

  ---WMMMUAC23 (0x820E3000 + 0x078)---

    MUAIFS_AC23[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC23[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC23[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC23[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC23_CURR_MUCW_AC23_ADDR           BN0_WF_ARB_TOP_WMMMUAC23_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC23_CURR_MUCW_AC23_MASK           0x1F000000                // CURR_MUCW_AC23[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC23_CURR_MUCW_AC23_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC23_MUCWMAX_AC23_ADDR             BN0_WF_ARB_TOP_WMMMUAC23_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC23_MUCWMAX_AC23_MASK             0x001F0000                // MUCWMAX_AC23[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC23_MUCWMAX_AC23_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC23_MUCWMIN_AC23_ADDR             BN0_WF_ARB_TOP_WMMMUAC23_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC23_MUCWMIN_AC23_MASK             0x00001F00                // MUCWMIN_AC23[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC23_MUCWMIN_AC23_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC23_MUAIFS_AC23_ADDR              BN0_WF_ARB_TOP_WMMMUAC23_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC23_MUAIFS_AC23_MASK              0x0000000F                // MUAIFS_AC23[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC23_MUAIFS_AC23_SHFT              0

/* =====================================================================================

  ---WMMMUAC30 (0x820E3000 + 0x07C)---

    MUAIFS_AC30[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC30[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC30[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC30[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC30_CURR_MUCW_AC30_ADDR           BN0_WF_ARB_TOP_WMMMUAC30_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC30_CURR_MUCW_AC30_MASK           0x1F000000                // CURR_MUCW_AC30[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC30_CURR_MUCW_AC30_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC30_MUCWMAX_AC30_ADDR             BN0_WF_ARB_TOP_WMMMUAC30_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC30_MUCWMAX_AC30_MASK             0x001F0000                // MUCWMAX_AC30[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC30_MUCWMAX_AC30_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC30_MUCWMIN_AC30_ADDR             BN0_WF_ARB_TOP_WMMMUAC30_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC30_MUCWMIN_AC30_MASK             0x00001F00                // MUCWMIN_AC30[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC30_MUCWMIN_AC30_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC30_MUAIFS_AC30_ADDR              BN0_WF_ARB_TOP_WMMMUAC30_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC30_MUAIFS_AC30_MASK              0x0000000F                // MUAIFS_AC30[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC30_MUAIFS_AC30_SHFT              0

/* =====================================================================================

  ---SCR (0x820E3000 + 0x080)---

    BCNQ_OP_MODE0[1..0]          - (RW) Beacon queue operation mode for BSSID0.
                                     00: Disable (STA mode)
                                     01: For AP mode, (BMC queue can only TX under this case after BCN.)
                                     10: Ad-Hoc mode
                                     11: Reserved
    BCNQ_OP_MODE1[3..2]          - (RW) Beacon queue operation mode for BSSID1.
                                     The same as BCNQ_OP_MODE0
    BCNQ_OP_MODE2[5..4]          - (RW) Beacon queue operation mode for BSSID2.
                                     The same as BCNQ_OP_MODE0
    BCNQ_OP_MODE3[7..6]          - (RW) Beacon queue operation mode for BSSID3.
                                     The same as BCNQ_OP_MODE0
    MAC0_TX_DIS[8]               - (RW) MAC to PHY Tx disable for DBDC0
    MAC0_RX_DIS[9]               - (RW) MAC to PHY Rx disable for DBDC0
    RESERVED10[11..10]           - (RO) Reserved bits
    CW_MAX_CHECK_EN[12]          - (RW)  xxx 
    BCN_DESC_SRCH_MISS_SEL[13]   - (RW)  xxx 
    NBCN_CTRL[14]                - (RW) Control the NAN Beacon TX priority.
                                     0: When set to 0, NBCN would have contention with other AC queues.
                                     1: After its HC NBCN frame should be the next TX frame, thus all other AC queues would be paused.
    TXOP_RE_MU[15]               - (RW) TXOP re-mu grouping select.
                                     When SU peer data empty (or MU primary data empty), scheme as follow
                                      0: re-choose peer user only, always don't MU
                                      1: re-choose peer user and band on new primary to choose new MU grouping.
    PLD_ENABLE_BF_TH[19..16]     - (RW) When Tx each queue's IFS + BFN < PLD_ENABLE_TH, MAC will assert MAC2PHY_PLD_ON to enable payload detect function. On the other hand, the MAC2PHY_PLD_ON must also satisfy PLF_ENABLE_NAV_TH, or the MAC2PHY_PLD_ON will deassert.
                                     The unit is slot.
                                     0: Disable (default)
                                     1~14: 1 slot 1~14 slots 
                                     15: always enable
    PLD_ENABLE_NAV_TH[23..20]    - (RW) When NAV_CNT <= PLD_ENABLE_NAV_TH, MAC will assert MAC2PHY_PLD_ON to enable payload detect function. On the other hand, the MAC2PHY_PLD_ON must also satisfy PLF_ENABLE_BF_TH, or the MAC2PHY_PLD_ON will deassert.
                                     The unit is 8 us.
                                     0~14: 1 slot (0~14) * 8 us 
                                     15: always enable
    BTIM_MTK_PPTARY[27..24]      - (RW) The switch of MTK proprietary mode for TIM broadcast for BSSID0~3. In MTK proprietary mode, the TTTT should be positive offset (>0) rather than TBTT, and BMC only active after TIM 
                                     broadcast. When offset is zero, the transmitted order of BCN and TIM broadcast depends on the packet en-queued order.
                                     0: Disable.
                                     1: Enable.
    BCNQ_EMPTY_CTRL[28]          - (RW) Beacon queue empty control. After TBTT/TTTT, HW start to Tx beacon/TIM broadcast. If SW still not insert beacon/TIM Broadcast into beacon queue, give up this beacon/TIM broadcast for this TBTT/TTTT or not.
                                     0: don't give up this TBTT/TTTT.
                                     1: give up this TBTT/TTTT.
    TTTT_BTIM_CTRL[29]           - (RW) Control the TTTT TIM Broadcast TX priority. This configuration is only used when BCNQ_OP_MODE is set to AP mode. (2'b01)
                                     0: When set to 0, TIM broadcast would have contention with other AC queues.
                                     1: After each TTTT, TIM broadcast frame should be the next TX frame, thus all other AC queues would be paused.
    TBTT_BCN_CTRL[30]            - (RW) Control the TBTT Beacon TX priority. This configuration is only used when BCNQ_OP_MODE is set to AP mode. (2'b01)
                                     0: When set to 0, BCN would have contention with other AC queues.
                                     1: After each TBTT, BCN frame should be the next TX frame, thus all other AC queues would be paused.
    TBTT_BM_CTRL[31]             - (RW) Control the TBTT BM TX priority. This configuration is only used when BCNQ_OP_MODE is set to AP mode. (2'b01)
                                     0: When set to 0, BM would have contention with other AC queues.
                                     1: After each success BCN frame, BM frame should be the next TX frame, thus all other AC queues would be paused.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_SCR_TBTT_BM_CTRL_ADDR                   BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_TBTT_BM_CTRL_MASK                   0x80000000                // TBTT_BM_CTRL[31]
#define BN0_WF_ARB_TOP_SCR_TBTT_BM_CTRL_SHFT                   31
#define BN0_WF_ARB_TOP_SCR_TBTT_BCN_CTRL_ADDR                  BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_TBTT_BCN_CTRL_MASK                  0x40000000                // TBTT_BCN_CTRL[30]
#define BN0_WF_ARB_TOP_SCR_TBTT_BCN_CTRL_SHFT                  30
#define BN0_WF_ARB_TOP_SCR_TTTT_BTIM_CTRL_ADDR                 BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_TTTT_BTIM_CTRL_MASK                 0x20000000                // TTTT_BTIM_CTRL[29]
#define BN0_WF_ARB_TOP_SCR_TTTT_BTIM_CTRL_SHFT                 29
#define BN0_WF_ARB_TOP_SCR_BCNQ_EMPTY_CTRL_ADDR                BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_BCNQ_EMPTY_CTRL_MASK                0x10000000                // BCNQ_EMPTY_CTRL[28]
#define BN0_WF_ARB_TOP_SCR_BCNQ_EMPTY_CTRL_SHFT                28
#define BN0_WF_ARB_TOP_SCR_BTIM_MTK_PPTARY_ADDR                BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_BTIM_MTK_PPTARY_MASK                0x0F000000                // BTIM_MTK_PPTARY[27..24]
#define BN0_WF_ARB_TOP_SCR_BTIM_MTK_PPTARY_SHFT                24
#define BN0_WF_ARB_TOP_SCR_PLD_ENABLE_NAV_TH_ADDR              BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_PLD_ENABLE_NAV_TH_MASK              0x00F00000                // PLD_ENABLE_NAV_TH[23..20]
#define BN0_WF_ARB_TOP_SCR_PLD_ENABLE_NAV_TH_SHFT              20
#define BN0_WF_ARB_TOP_SCR_PLD_ENABLE_BF_TH_ADDR               BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_PLD_ENABLE_BF_TH_MASK               0x000F0000                // PLD_ENABLE_BF_TH[19..16]
#define BN0_WF_ARB_TOP_SCR_PLD_ENABLE_BF_TH_SHFT               16
#define BN0_WF_ARB_TOP_SCR_TXOP_RE_MU_ADDR                     BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_TXOP_RE_MU_MASK                     0x00008000                // TXOP_RE_MU[15]
#define BN0_WF_ARB_TOP_SCR_TXOP_RE_MU_SHFT                     15
#define BN0_WF_ARB_TOP_SCR_NBCN_CTRL_ADDR                      BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_NBCN_CTRL_MASK                      0x00004000                // NBCN_CTRL[14]
#define BN0_WF_ARB_TOP_SCR_NBCN_CTRL_SHFT                      14
#define BN0_WF_ARB_TOP_SCR_BCN_DESC_SRCH_MISS_SEL_ADDR         BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_BCN_DESC_SRCH_MISS_SEL_MASK         0x00002000                // BCN_DESC_SRCH_MISS_SEL[13]
#define BN0_WF_ARB_TOP_SCR_BCN_DESC_SRCH_MISS_SEL_SHFT         13
#define BN0_WF_ARB_TOP_SCR_CW_MAX_CHECK_EN_ADDR                BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_CW_MAX_CHECK_EN_MASK                0x00001000                // CW_MAX_CHECK_EN[12]
#define BN0_WF_ARB_TOP_SCR_CW_MAX_CHECK_EN_SHFT                12
#define BN0_WF_ARB_TOP_SCR_MAC0_RX_DIS_ADDR                    BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_MAC0_RX_DIS_MASK                    0x00000200                // MAC0_RX_DIS[9]
#define BN0_WF_ARB_TOP_SCR_MAC0_RX_DIS_SHFT                    9
#define BN0_WF_ARB_TOP_SCR_MAC0_TX_DIS_ADDR                    BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_MAC0_TX_DIS_MASK                    0x00000100                // MAC0_TX_DIS[8]
#define BN0_WF_ARB_TOP_SCR_MAC0_TX_DIS_SHFT                    8
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE3_ADDR                  BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE3_MASK                  0x000000C0                // BCNQ_OP_MODE3[7..6]
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE3_SHFT                  6
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE2_ADDR                  BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE2_MASK                  0x00000030                // BCNQ_OP_MODE2[5..4]
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE2_SHFT                  4
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE1_ADDR                  BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE1_MASK                  0x0000000C                // BCNQ_OP_MODE1[3..2]
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE1_SHFT                  2
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE0_ADDR                  BN0_WF_ARB_TOP_SCR_ADDR
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE0_MASK                  0x00000003                // BCNQ_OP_MODE0[1..0]
#define BN0_WF_ARB_TOP_SCR_BCNQ_OP_MODE0_SHFT                  0

/* =====================================================================================

  ---WMMMUAC31 (0x820E3000 + 0x084)---

    MUAIFS_AC31[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC31[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC31[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC31[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC31_CURR_MUCW_AC31_ADDR           BN0_WF_ARB_TOP_WMMMUAC31_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC31_CURR_MUCW_AC31_MASK           0x1F000000                // CURR_MUCW_AC31[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC31_CURR_MUCW_AC31_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC31_MUCWMAX_AC31_ADDR             BN0_WF_ARB_TOP_WMMMUAC31_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC31_MUCWMAX_AC31_MASK             0x001F0000                // MUCWMAX_AC31[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC31_MUCWMAX_AC31_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC31_MUCWMIN_AC31_ADDR             BN0_WF_ARB_TOP_WMMMUAC31_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC31_MUCWMIN_AC31_MASK             0x00001F00                // MUCWMIN_AC31[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC31_MUCWMIN_AC31_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC31_MUAIFS_AC31_ADDR              BN0_WF_ARB_TOP_WMMMUAC31_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC31_MUAIFS_AC31_MASK              0x0000000F                // MUAIFS_AC31[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC31_MUAIFS_AC31_SHFT              0

/* =====================================================================================

  ---WMMMUAC32 (0x820E3000 + 0x088)---

    MUAIFS_AC32[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC32[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC32[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC32[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC32_CURR_MUCW_AC32_ADDR           BN0_WF_ARB_TOP_WMMMUAC32_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC32_CURR_MUCW_AC32_MASK           0x1F000000                // CURR_MUCW_AC32[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC32_CURR_MUCW_AC32_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC32_MUCWMAX_AC32_ADDR             BN0_WF_ARB_TOP_WMMMUAC32_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC32_MUCWMAX_AC32_MASK             0x001F0000                // MUCWMAX_AC32[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC32_MUCWMAX_AC32_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC32_MUCWMIN_AC32_ADDR             BN0_WF_ARB_TOP_WMMMUAC32_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC32_MUCWMIN_AC32_MASK             0x00001F00                // MUCWMIN_AC32[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC32_MUCWMIN_AC32_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC32_MUAIFS_AC32_ADDR              BN0_WF_ARB_TOP_WMMMUAC32_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC32_MUAIFS_AC32_MASK              0x0000000F                // MUAIFS_AC32[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC32_MUAIFS_AC32_SHFT              0

/* =====================================================================================

  ---WMMMUAC33 (0x820E3000 + 0x08C)---

    MUAIFS_AC33[3..0]            - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    MUCWMIN_AC33[12..8]          - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    MUCWMAX_AC33[20..16]         - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_MUCW_AC33[28..24]       - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMMUAC33_CURR_MUCW_AC33_ADDR           BN0_WF_ARB_TOP_WMMMUAC33_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC33_CURR_MUCW_AC33_MASK           0x1F000000                // CURR_MUCW_AC33[28..24]
#define BN0_WF_ARB_TOP_WMMMUAC33_CURR_MUCW_AC33_SHFT           24
#define BN0_WF_ARB_TOP_WMMMUAC33_MUCWMAX_AC33_ADDR             BN0_WF_ARB_TOP_WMMMUAC33_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC33_MUCWMAX_AC33_MASK             0x001F0000                // MUCWMAX_AC33[20..16]
#define BN0_WF_ARB_TOP_WMMMUAC33_MUCWMAX_AC33_SHFT             16
#define BN0_WF_ARB_TOP_WMMMUAC33_MUCWMIN_AC33_ADDR             BN0_WF_ARB_TOP_WMMMUAC33_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC33_MUCWMIN_AC33_MASK             0x00001F00                // MUCWMIN_AC33[12..8]
#define BN0_WF_ARB_TOP_WMMMUAC33_MUCWMIN_AC33_SHFT             8
#define BN0_WF_ARB_TOP_WMMMUAC33_MUAIFS_AC33_ADDR              BN0_WF_ARB_TOP_WMMMUAC33_ADDR
#define BN0_WF_ARB_TOP_WMMMUAC33_MUAIFS_AC33_MASK              0x0000000F                // MUAIFS_AC33[3..0]
#define BN0_WF_ARB_TOP_WMMMUAC33_MUAIFS_AC33_SHFT              0

/* =====================================================================================

  ---SPTO0 (0x820E3000 + 0x0A0)---

    BCN_SP_TIMEOUT_0[6..0]       - (RW) Timeout count of BCN service period for BSSID0 and BSSID0_1~15. Only enabled by BCN_SP_TIMEOUT_EN_0. 
                                     If BCN service period is 0, the count is 0.
                                     If BCN service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BCN_SP_TIMEOUT_0, the service period signal to ARB_PTA will be masked off.
    BCN_SP_TIMEOUT_EN_0[7]       - (RW) Enable of BCN service period timeout counting for BSSID0 and BSSID0_1~15.
    BCN_BMC_SP_TIMEOUT_0[14..8]  - (RW) Timeout count of BMC after BCN service period for BSSID0. Only enabled by BMC_BCN_SP_TIMEOUT_EN_0. 
                                     If BCN_BMC service period is 0, the count is 0.
                                     If BCN_BMC service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BCN_BMC_SP_TIMEOUT_0, the service period signal to ARB_PTA will be masked off.
    BCN_BMC_SP_TIMEOUT_EN_0[15]  - (RW) Enable of BMC after BCN service period timeout counting for BSSID0.
    BTIM_SP_TIMEOUT_0[22..16]    - (RW) Timeout count of BTIM service period for BSSID0 and BSSID0_1~15. Only enabled by BTIM_SP_TIMEOUT_EN_0. 
                                     If BTIM service period is 0, the count is 0.
                                     If BTIM service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BTIM_SP_TIMEOUT_0, the service period signal to ARB_PTA will be masked off.
    BTIM_SP_TIMEOUT_EN_0[23]     - (RW) Enable of BTIM service period timeout counting for BSSID0 and BSSID0_1~15.
    BTIM_BMC_SP_TIMEOUT_0[30..24] - (RW) Timeout count of BMC after BTIM service period for BSSID0. Only enabled by BMC_BTIM_SP_TIMEOUT_EN_0. 
                                     If BTIM_BMC service period is 0, the count is 0.
                                     If BTIM_BMC service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BTIM_BMC_SP_TIMEOUT_0, the service period signal to ARB_PTA will be masked off.
    BTIM_BMC_SP_TIMEOUT_EN_0[31] - (RW) Enable of BMC after BTIM service period timeout counting for BSSID0.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_SPTO0_BTIM_BMC_SP_TIMEOUT_EN_0_ADDR     BN0_WF_ARB_TOP_SPTO0_ADDR
#define BN0_WF_ARB_TOP_SPTO0_BTIM_BMC_SP_TIMEOUT_EN_0_MASK     0x80000000                // BTIM_BMC_SP_TIMEOUT_EN_0[31]
#define BN0_WF_ARB_TOP_SPTO0_BTIM_BMC_SP_TIMEOUT_EN_0_SHFT     31
#define BN0_WF_ARB_TOP_SPTO0_BTIM_BMC_SP_TIMEOUT_0_ADDR        BN0_WF_ARB_TOP_SPTO0_ADDR
#define BN0_WF_ARB_TOP_SPTO0_BTIM_BMC_SP_TIMEOUT_0_MASK        0x7F000000                // BTIM_BMC_SP_TIMEOUT_0[30..24]
#define BN0_WF_ARB_TOP_SPTO0_BTIM_BMC_SP_TIMEOUT_0_SHFT        24
#define BN0_WF_ARB_TOP_SPTO0_BTIM_SP_TIMEOUT_EN_0_ADDR         BN0_WF_ARB_TOP_SPTO0_ADDR
#define BN0_WF_ARB_TOP_SPTO0_BTIM_SP_TIMEOUT_EN_0_MASK         0x00800000                // BTIM_SP_TIMEOUT_EN_0[23]
#define BN0_WF_ARB_TOP_SPTO0_BTIM_SP_TIMEOUT_EN_0_SHFT         23
#define BN0_WF_ARB_TOP_SPTO0_BTIM_SP_TIMEOUT_0_ADDR            BN0_WF_ARB_TOP_SPTO0_ADDR
#define BN0_WF_ARB_TOP_SPTO0_BTIM_SP_TIMEOUT_0_MASK            0x007F0000                // BTIM_SP_TIMEOUT_0[22..16]
#define BN0_WF_ARB_TOP_SPTO0_BTIM_SP_TIMEOUT_0_SHFT            16
#define BN0_WF_ARB_TOP_SPTO0_BCN_BMC_SP_TIMEOUT_EN_0_ADDR      BN0_WF_ARB_TOP_SPTO0_ADDR
#define BN0_WF_ARB_TOP_SPTO0_BCN_BMC_SP_TIMEOUT_EN_0_MASK      0x00008000                // BCN_BMC_SP_TIMEOUT_EN_0[15]
#define BN0_WF_ARB_TOP_SPTO0_BCN_BMC_SP_TIMEOUT_EN_0_SHFT      15
#define BN0_WF_ARB_TOP_SPTO0_BCN_BMC_SP_TIMEOUT_0_ADDR         BN0_WF_ARB_TOP_SPTO0_ADDR
#define BN0_WF_ARB_TOP_SPTO0_BCN_BMC_SP_TIMEOUT_0_MASK         0x00007F00                // BCN_BMC_SP_TIMEOUT_0[14..8]
#define BN0_WF_ARB_TOP_SPTO0_BCN_BMC_SP_TIMEOUT_0_SHFT         8
#define BN0_WF_ARB_TOP_SPTO0_BCN_SP_TIMEOUT_EN_0_ADDR          BN0_WF_ARB_TOP_SPTO0_ADDR
#define BN0_WF_ARB_TOP_SPTO0_BCN_SP_TIMEOUT_EN_0_MASK          0x00000080                // BCN_SP_TIMEOUT_EN_0[7]
#define BN0_WF_ARB_TOP_SPTO0_BCN_SP_TIMEOUT_EN_0_SHFT          7
#define BN0_WF_ARB_TOP_SPTO0_BCN_SP_TIMEOUT_0_ADDR             BN0_WF_ARB_TOP_SPTO0_ADDR
#define BN0_WF_ARB_TOP_SPTO0_BCN_SP_TIMEOUT_0_MASK             0x0000007F                // BCN_SP_TIMEOUT_0[6..0]
#define BN0_WF_ARB_TOP_SPTO0_BCN_SP_TIMEOUT_0_SHFT             0

/* =====================================================================================

  ---SPTO1 (0x820E3000 + 0x0A4)---

    BCN_SP_TIMEOUT_1[6..0]       - (RW) Timeout count of BCN service period for BSSID1. Only enabled by BCN_SP_TIMEOUT_EN_1. 
                                     If BCN service period is 0, the count is 0.
                                     If BCN service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BCN_SP_TIMEOUT_1, the service period signal to ARB_PTA will be masked off.
    BCN_SP_TIMEOUT_EN_1[7]       - (RW) Enable of BCN service period timeout counting for BSSID1.
    BCN_BMC_SP_TIMEOUT_1[14..8]  - (RW) Timeout count of BMC after BCN service period for BSSID1. Only enabled by BMC_BCN_SP_TIMEOUT_EN_1. 
                                     If BCN_BMC service period is 0, the count is 0.
                                     If BCN_BMC service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BCN_BMC_SP_TIMEOUT_1, the service period signal to ARB_PTA will be masked off.
    BCN_BMC_SP_TIMEOUT_EN_1[15]  - (RW) Enable of BMC after BCN service period timeout counting for BSSID1.
    BTIM_SP_TIMEOUT_1[22..16]    - (RW) Timeout count of BTIM service period for BSSID1. Only enabled by BTIM_SP_TIMEOUT_EN_1. 
                                     If BTIM service period is 0, the count is 0.
                                     If BTIM service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BTIM_SP_TIMEOUT_1, the service period signal to ARB_PTA will be masked off.
    BTIM_SP_TIMEOUT_EN_1[23]     - (RW) Enable of BTIM service period timeout counting for BSSID1.
    BTIM_BMC_SP_TIMEOUT_1[30..24] - (RW) Timeout count of BMC after BTIM service period for BSSID1. Only enabled by BMC_BTIM_SP_TIMEOUT_EN_1. 
                                     If BTIM_BMC service period is 0, the count is 0.
                                     If BTIM_BMC service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BTIM_BMC_SP_TIMEOUT_1, the service period signal to ARB_PTA will be masked off.
    BTIM_BMC_SP_TIMEOUT_EN_1[31] - (RW) Enable of BMC after BTIM service period timeout counting for BSSID1.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_SPTO1_BTIM_BMC_SP_TIMEOUT_EN_1_ADDR     BN0_WF_ARB_TOP_SPTO1_ADDR
#define BN0_WF_ARB_TOP_SPTO1_BTIM_BMC_SP_TIMEOUT_EN_1_MASK     0x80000000                // BTIM_BMC_SP_TIMEOUT_EN_1[31]
#define BN0_WF_ARB_TOP_SPTO1_BTIM_BMC_SP_TIMEOUT_EN_1_SHFT     31
#define BN0_WF_ARB_TOP_SPTO1_BTIM_BMC_SP_TIMEOUT_1_ADDR        BN0_WF_ARB_TOP_SPTO1_ADDR
#define BN0_WF_ARB_TOP_SPTO1_BTIM_BMC_SP_TIMEOUT_1_MASK        0x7F000000                // BTIM_BMC_SP_TIMEOUT_1[30..24]
#define BN0_WF_ARB_TOP_SPTO1_BTIM_BMC_SP_TIMEOUT_1_SHFT        24
#define BN0_WF_ARB_TOP_SPTO1_BTIM_SP_TIMEOUT_EN_1_ADDR         BN0_WF_ARB_TOP_SPTO1_ADDR
#define BN0_WF_ARB_TOP_SPTO1_BTIM_SP_TIMEOUT_EN_1_MASK         0x00800000                // BTIM_SP_TIMEOUT_EN_1[23]
#define BN0_WF_ARB_TOP_SPTO1_BTIM_SP_TIMEOUT_EN_1_SHFT         23
#define BN0_WF_ARB_TOP_SPTO1_BTIM_SP_TIMEOUT_1_ADDR            BN0_WF_ARB_TOP_SPTO1_ADDR
#define BN0_WF_ARB_TOP_SPTO1_BTIM_SP_TIMEOUT_1_MASK            0x007F0000                // BTIM_SP_TIMEOUT_1[22..16]
#define BN0_WF_ARB_TOP_SPTO1_BTIM_SP_TIMEOUT_1_SHFT            16
#define BN0_WF_ARB_TOP_SPTO1_BCN_BMC_SP_TIMEOUT_EN_1_ADDR      BN0_WF_ARB_TOP_SPTO1_ADDR
#define BN0_WF_ARB_TOP_SPTO1_BCN_BMC_SP_TIMEOUT_EN_1_MASK      0x00008000                // BCN_BMC_SP_TIMEOUT_EN_1[15]
#define BN0_WF_ARB_TOP_SPTO1_BCN_BMC_SP_TIMEOUT_EN_1_SHFT      15
#define BN0_WF_ARB_TOP_SPTO1_BCN_BMC_SP_TIMEOUT_1_ADDR         BN0_WF_ARB_TOP_SPTO1_ADDR
#define BN0_WF_ARB_TOP_SPTO1_BCN_BMC_SP_TIMEOUT_1_MASK         0x00007F00                // BCN_BMC_SP_TIMEOUT_1[14..8]
#define BN0_WF_ARB_TOP_SPTO1_BCN_BMC_SP_TIMEOUT_1_SHFT         8
#define BN0_WF_ARB_TOP_SPTO1_BCN_SP_TIMEOUT_EN_1_ADDR          BN0_WF_ARB_TOP_SPTO1_ADDR
#define BN0_WF_ARB_TOP_SPTO1_BCN_SP_TIMEOUT_EN_1_MASK          0x00000080                // BCN_SP_TIMEOUT_EN_1[7]
#define BN0_WF_ARB_TOP_SPTO1_BCN_SP_TIMEOUT_EN_1_SHFT          7
#define BN0_WF_ARB_TOP_SPTO1_BCN_SP_TIMEOUT_1_ADDR             BN0_WF_ARB_TOP_SPTO1_ADDR
#define BN0_WF_ARB_TOP_SPTO1_BCN_SP_TIMEOUT_1_MASK             0x0000007F                // BCN_SP_TIMEOUT_1[6..0]
#define BN0_WF_ARB_TOP_SPTO1_BCN_SP_TIMEOUT_1_SHFT             0

/* =====================================================================================

  ---SPTO2 (0x820E3000 + 0x0A8)---

    BCN_SP_TIMEOUT_2[6..0]       - (RW) Timeout count of BCN service period for BSSID2. Only enabled by BCN_SP_TIMEOUT_EN_2. 
                                     If BCN service period is 0, the count is 0.
                                     If BCN service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BCN_SP_TIMEOUT_2, the service period signal to ARB_PTA will be masked off.
    BCN_SP_TIMEOUT_EN_2[7]       - (RW) Enable of BCN service period timeout counting for BSSID2.
    BCN_BMC_SP_TIMEOUT_2[14..8]  - (RW) Timeout count of BMC after BCN service period for BSSID2. Only enabled by BMC_BCN_SP_TIMEOUT_EN_2. 
                                     If BCN_BMC service period is 0, the count is 0.
                                     If BCN_BMC service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BCN_BMC_SP_TIMEOUT_2, the service period signal to ARB_PTA will be masked off.
    BCN_BMC_SP_TIMEOUT_EN_2[15]  - (RW) Enable of BMC after BCN service period timeout counting for BSSID2.
    BTIM_SP_TIMEOUT_2[22..16]    - (RW) Timeout count of BTIM service period for BSSID2. Only enabled by BTIM_SP_TIMEOUT_EN_2. 
                                     If BTIM service period is 0, the count is 0.
                                     If BTIM service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BTIM_SP_TIMEOUT_2, the service period signal to ARB_PTA will be masked off.
    BTIM_SP_TIMEOUT_EN_2[23]     - (RW) Enable of BTIM service period timeout counting for BSSID2.
    BTIM_BMC_SP_TIMEOUT_2[30..24] - (RW) Timeout count of BMC after BTIM service period for BSSID2. Only enabled by BMC_BTIM_SP_TIMEOUT_EN_2. 
                                     If BTIM_BMC service period is 0, the count is 0.
                                     If BTIM_BMC service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BTIM_BMC_SP_TIMEOUT_2, the service period signal to ARB_PTA will be masked off.
    BTIM_BMC_SP_TIMEOUT_EN_2[31] - (RW) Enable of BMC after BTIM service period timeout counting for BSSID2.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_SPTO2_BTIM_BMC_SP_TIMEOUT_EN_2_ADDR     BN0_WF_ARB_TOP_SPTO2_ADDR
#define BN0_WF_ARB_TOP_SPTO2_BTIM_BMC_SP_TIMEOUT_EN_2_MASK     0x80000000                // BTIM_BMC_SP_TIMEOUT_EN_2[31]
#define BN0_WF_ARB_TOP_SPTO2_BTIM_BMC_SP_TIMEOUT_EN_2_SHFT     31
#define BN0_WF_ARB_TOP_SPTO2_BTIM_BMC_SP_TIMEOUT_2_ADDR        BN0_WF_ARB_TOP_SPTO2_ADDR
#define BN0_WF_ARB_TOP_SPTO2_BTIM_BMC_SP_TIMEOUT_2_MASK        0x7F000000                // BTIM_BMC_SP_TIMEOUT_2[30..24]
#define BN0_WF_ARB_TOP_SPTO2_BTIM_BMC_SP_TIMEOUT_2_SHFT        24
#define BN0_WF_ARB_TOP_SPTO2_BTIM_SP_TIMEOUT_EN_2_ADDR         BN0_WF_ARB_TOP_SPTO2_ADDR
#define BN0_WF_ARB_TOP_SPTO2_BTIM_SP_TIMEOUT_EN_2_MASK         0x00800000                // BTIM_SP_TIMEOUT_EN_2[23]
#define BN0_WF_ARB_TOP_SPTO2_BTIM_SP_TIMEOUT_EN_2_SHFT         23
#define BN0_WF_ARB_TOP_SPTO2_BTIM_SP_TIMEOUT_2_ADDR            BN0_WF_ARB_TOP_SPTO2_ADDR
#define BN0_WF_ARB_TOP_SPTO2_BTIM_SP_TIMEOUT_2_MASK            0x007F0000                // BTIM_SP_TIMEOUT_2[22..16]
#define BN0_WF_ARB_TOP_SPTO2_BTIM_SP_TIMEOUT_2_SHFT            16
#define BN0_WF_ARB_TOP_SPTO2_BCN_BMC_SP_TIMEOUT_EN_2_ADDR      BN0_WF_ARB_TOP_SPTO2_ADDR
#define BN0_WF_ARB_TOP_SPTO2_BCN_BMC_SP_TIMEOUT_EN_2_MASK      0x00008000                // BCN_BMC_SP_TIMEOUT_EN_2[15]
#define BN0_WF_ARB_TOP_SPTO2_BCN_BMC_SP_TIMEOUT_EN_2_SHFT      15
#define BN0_WF_ARB_TOP_SPTO2_BCN_BMC_SP_TIMEOUT_2_ADDR         BN0_WF_ARB_TOP_SPTO2_ADDR
#define BN0_WF_ARB_TOP_SPTO2_BCN_BMC_SP_TIMEOUT_2_MASK         0x00007F00                // BCN_BMC_SP_TIMEOUT_2[14..8]
#define BN0_WF_ARB_TOP_SPTO2_BCN_BMC_SP_TIMEOUT_2_SHFT         8
#define BN0_WF_ARB_TOP_SPTO2_BCN_SP_TIMEOUT_EN_2_ADDR          BN0_WF_ARB_TOP_SPTO2_ADDR
#define BN0_WF_ARB_TOP_SPTO2_BCN_SP_TIMEOUT_EN_2_MASK          0x00000080                // BCN_SP_TIMEOUT_EN_2[7]
#define BN0_WF_ARB_TOP_SPTO2_BCN_SP_TIMEOUT_EN_2_SHFT          7
#define BN0_WF_ARB_TOP_SPTO2_BCN_SP_TIMEOUT_2_ADDR             BN0_WF_ARB_TOP_SPTO2_ADDR
#define BN0_WF_ARB_TOP_SPTO2_BCN_SP_TIMEOUT_2_MASK             0x0000007F                // BCN_SP_TIMEOUT_2[6..0]
#define BN0_WF_ARB_TOP_SPTO2_BCN_SP_TIMEOUT_2_SHFT             0

/* =====================================================================================

  ---SPTO3 (0x820E3000 + 0x0AC)---

    BCN_SP_TIMEOUT_3[6..0]       - (RW) Timeout count of BCN service period for BSSID3. Only enabled by BCN_SP_TIMEOUT_EN_3. 
                                     If BCN service period is 0, the count is 0.
                                     If BCN service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BCN_SP_TIMEOUT_3, the service period signal to ARB_PTA will be masked off.
    BCN_SP_TIMEOUT_EN_3[7]       - (RW) Enable of BCN service period timeout counting for BSSID3.
    BCN_BMC_SP_TIMEOUT_3[14..8]  - (RW) Timeout count of BMC after BCN service period for BSSID3. Only enabled by BMC_BCN_SP_TIMEOUT_EN_3. 
                                     If BCN_BMC service period is 0, the count is 0.
                                     If BCN_BMC service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BCN_BMC_SP_TIMEOUT_3, the service period signal to ARB_PTA will be masked off.
    BCN_BMC_SP_TIMEOUT_EN_3[15]  - (RW) Enable of BMC after BCN service period timeout counting for BSSID3.
    BTIM_SP_TIMEOUT_3[22..16]    - (RW) Timeout count of BTIM service period for BSSID3. Only enabled by BTIM_SP_TIMEOUT_EN_3. 
                                     If BTIM service period is 0, the count is 0.
                                     If BTIM service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BTIM_SP_TIMEOUT_3, the service period signal to ARB_PTA will be masked off.
    BTIM_SP_TIMEOUT_EN_3[23]     - (RW) Enable of BTIM service period timeout counting for BSSID3.
    BTIM_BMC_SP_TIMEOUT_3[30..24] - (RW) Timeout count of BMC after BTIM service period for BSSID3. Only enabled by BMC_BTIM_SP_TIMEOUT_EN_3. 
                                     If BTIM_BMC service period is 0, the count is 0.
                                     If BTIM_BMC service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches BTIM_BMC_SP_TIMEOUT_3, the service period signal to ARB_PTA will be masked off.
    BTIM_BMC_SP_TIMEOUT_EN_3[31] - (RW) Enable of BMC after BTIM service period timeout counting for BSSID3.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_SPTO3_BTIM_BMC_SP_TIMEOUT_EN_3_ADDR     BN0_WF_ARB_TOP_SPTO3_ADDR
#define BN0_WF_ARB_TOP_SPTO3_BTIM_BMC_SP_TIMEOUT_EN_3_MASK     0x80000000                // BTIM_BMC_SP_TIMEOUT_EN_3[31]
#define BN0_WF_ARB_TOP_SPTO3_BTIM_BMC_SP_TIMEOUT_EN_3_SHFT     31
#define BN0_WF_ARB_TOP_SPTO3_BTIM_BMC_SP_TIMEOUT_3_ADDR        BN0_WF_ARB_TOP_SPTO3_ADDR
#define BN0_WF_ARB_TOP_SPTO3_BTIM_BMC_SP_TIMEOUT_3_MASK        0x7F000000                // BTIM_BMC_SP_TIMEOUT_3[30..24]
#define BN0_WF_ARB_TOP_SPTO3_BTIM_BMC_SP_TIMEOUT_3_SHFT        24
#define BN0_WF_ARB_TOP_SPTO3_BTIM_SP_TIMEOUT_EN_3_ADDR         BN0_WF_ARB_TOP_SPTO3_ADDR
#define BN0_WF_ARB_TOP_SPTO3_BTIM_SP_TIMEOUT_EN_3_MASK         0x00800000                // BTIM_SP_TIMEOUT_EN_3[23]
#define BN0_WF_ARB_TOP_SPTO3_BTIM_SP_TIMEOUT_EN_3_SHFT         23
#define BN0_WF_ARB_TOP_SPTO3_BTIM_SP_TIMEOUT_3_ADDR            BN0_WF_ARB_TOP_SPTO3_ADDR
#define BN0_WF_ARB_TOP_SPTO3_BTIM_SP_TIMEOUT_3_MASK            0x007F0000                // BTIM_SP_TIMEOUT_3[22..16]
#define BN0_WF_ARB_TOP_SPTO3_BTIM_SP_TIMEOUT_3_SHFT            16
#define BN0_WF_ARB_TOP_SPTO3_BCN_BMC_SP_TIMEOUT_EN_3_ADDR      BN0_WF_ARB_TOP_SPTO3_ADDR
#define BN0_WF_ARB_TOP_SPTO3_BCN_BMC_SP_TIMEOUT_EN_3_MASK      0x00008000                // BCN_BMC_SP_TIMEOUT_EN_3[15]
#define BN0_WF_ARB_TOP_SPTO3_BCN_BMC_SP_TIMEOUT_EN_3_SHFT      15
#define BN0_WF_ARB_TOP_SPTO3_BCN_BMC_SP_TIMEOUT_3_ADDR         BN0_WF_ARB_TOP_SPTO3_ADDR
#define BN0_WF_ARB_TOP_SPTO3_BCN_BMC_SP_TIMEOUT_3_MASK         0x00007F00                // BCN_BMC_SP_TIMEOUT_3[14..8]
#define BN0_WF_ARB_TOP_SPTO3_BCN_BMC_SP_TIMEOUT_3_SHFT         8
#define BN0_WF_ARB_TOP_SPTO3_BCN_SP_TIMEOUT_EN_3_ADDR          BN0_WF_ARB_TOP_SPTO3_ADDR
#define BN0_WF_ARB_TOP_SPTO3_BCN_SP_TIMEOUT_EN_3_MASK          0x00000080                // BCN_SP_TIMEOUT_EN_3[7]
#define BN0_WF_ARB_TOP_SPTO3_BCN_SP_TIMEOUT_EN_3_SHFT          7
#define BN0_WF_ARB_TOP_SPTO3_BCN_SP_TIMEOUT_3_ADDR             BN0_WF_ARB_TOP_SPTO3_ADDR
#define BN0_WF_ARB_TOP_SPTO3_BCN_SP_TIMEOUT_3_MASK             0x0000007F                // BCN_SP_TIMEOUT_3[6..0]
#define BN0_WF_ARB_TOP_SPTO3_BCN_SP_TIMEOUT_3_SHFT             0

/* =====================================================================================

  ---SPTOW (0x820E3000 + 0x0B0)---

    WHOLE_SP_TIMEOUT_0[6..0]     - (RW) Timeout count of whole service period for BSSID0 and BSSID0_1~15. Only enabled by WHOLE_SP_TIMEOUT_EN_0. 
                                     Whole service period = BCN_SP | BMC_BCN_SP | BTIM_SP | BMC_BTIM_SP. 
                                     If Whole service period is 0, the count is 0.
                                     If Whole service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches WHOLE_SP_TIMEOUT_0, the service period signal to ARB_PTA will be masked off.
    WHOLE_SP_TIMEOUT_EN_0[7]     - (RW) Enable of Whole service period timeout counting for BSSID0 and BSSID0_1~15.
    WHOLE_SP_TIMEOUT_1[14..8]    - (RW) Timeout count of whole service period for BSSID1. Only enabled by WHOLE_SP_TIMEOUT_EN_1. 
                                     Whole service period = BCN_SP | BMC_BCN_SP | BTIM_SP | BMC_BTIM_SP. 
                                     If Whole service period is 0, the count is 0.
                                     If Whole service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches WHOLE_SP_TIMEOUT_1, the service period signal to ARB_PTA will be masked off.
    WHOLE_SP_TIMEOUT_EN_1[15]    - (RW) Enable of Whole service period timeout counting for BSSID1.
    WHOLE_SP_TIMEOUT_2[22..16]   - (RW) Timeout count of whole service period for BSSID2. Only enabled by WHOLE_SP_TIMEOUT_EN_2. 
                                     Whole service period = BCN_SP | BMC_BCN_SP | BTIM_SP | BMC_BTIM_SP. 
                                     If Whole service period is 0, the count is 0.
                                     If Whole service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches WHOLE_SP_TIMEOUT_2, the service period signal to ARB_PTA will be masked off.
    WHOLE_SP_TIMEOUT_EN_2[23]    - (RW) Enable of Whole service period timeout counting for BSSID2.
    WHOLE_SP_TIMEOUT_3[30..24]   - (RW) Timeout count of whole service period for BSSID3. Only enabled by WHOLE_SP_TIMEOUT_EN_3. 
                                     Whole service period = BCN_SP | BMC_BCN_SP | BTIM_SP | BMC_BTIM_SP. 
                                     If Whole service period is 0, the count is 0.
                                     If Whole service period is 1, the count increments by 1 at each LP_1TU_TICK.
                                     If the count reaches WHOLE_SP_TIMEOUT_3, the service period signal to ARB_PTA will be masked off.
    WHOLE_SP_TIMEOUT_EN_3[31]    - (RW) Enable of Whole service period timeout counting for BSSID3.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_3_ADDR        BN0_WF_ARB_TOP_SPTOW_ADDR
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_3_MASK        0x80000000                // WHOLE_SP_TIMEOUT_EN_3[31]
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_3_SHFT        31
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_3_ADDR           BN0_WF_ARB_TOP_SPTOW_ADDR
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_3_MASK           0x7F000000                // WHOLE_SP_TIMEOUT_3[30..24]
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_3_SHFT           24
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_2_ADDR        BN0_WF_ARB_TOP_SPTOW_ADDR
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_2_MASK        0x00800000                // WHOLE_SP_TIMEOUT_EN_2[23]
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_2_SHFT        23
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_2_ADDR           BN0_WF_ARB_TOP_SPTOW_ADDR
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_2_MASK           0x007F0000                // WHOLE_SP_TIMEOUT_2[22..16]
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_2_SHFT           16
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_1_ADDR        BN0_WF_ARB_TOP_SPTOW_ADDR
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_1_MASK        0x00008000                // WHOLE_SP_TIMEOUT_EN_1[15]
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_1_SHFT        15
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_1_ADDR           BN0_WF_ARB_TOP_SPTOW_ADDR
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_1_MASK           0x00007F00                // WHOLE_SP_TIMEOUT_1[14..8]
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_1_SHFT           8
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_0_ADDR        BN0_WF_ARB_TOP_SPTOW_ADDR
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_0_MASK        0x00000080                // WHOLE_SP_TIMEOUT_EN_0[7]
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_EN_0_SHFT        7
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_0_ADDR           BN0_WF_ARB_TOP_SPTOW_ADDR
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_0_MASK           0x0000007F                // WHOLE_SP_TIMEOUT_0[6..0]
#define BN0_WF_ARB_TOP_SPTOW_WHOLE_SP_TIMEOUT_0_SHFT           0

/* =====================================================================================

  ---BMCCR6 (0x820E3000 + 0x0B4)---

    BMC_STRAIGHTFORWARD0_0[0]    - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD1[1]      - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD2[2]      - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD3[3]      - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    RESERVED4[16..4]             - (RO) Reserved bits
    BMC_STRAIGHTFORWARD0_1[17]   - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_2[18]   - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_3[19]   - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_4[20]   - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_5[21]   - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_6[22]   - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_7[23]   - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_8[24]   - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_9[25]   - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_10[26]  - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_11[27]  - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_12[28]  - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_13[29]  - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_14[30]  - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.
    BMC_STRAIGHTFORWARD0_15[31]  - (RW) 0: Only TX BMC after BCN of BTIM.
                                     1: TX BMC anytime.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_15_ADDR     BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_15_MASK     0x80000000                // BMC_STRAIGHTFORWARD0_15[31]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_15_SHFT     31
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_14_ADDR     BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_14_MASK     0x40000000                // BMC_STRAIGHTFORWARD0_14[30]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_14_SHFT     30
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_13_ADDR     BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_13_MASK     0x20000000                // BMC_STRAIGHTFORWARD0_13[29]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_13_SHFT     29
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_12_ADDR     BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_12_MASK     0x10000000                // BMC_STRAIGHTFORWARD0_12[28]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_12_SHFT     28
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_11_ADDR     BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_11_MASK     0x08000000                // BMC_STRAIGHTFORWARD0_11[27]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_11_SHFT     27
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_10_ADDR     BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_10_MASK     0x04000000                // BMC_STRAIGHTFORWARD0_10[26]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_10_SHFT     26
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_9_ADDR      BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_9_MASK      0x02000000                // BMC_STRAIGHTFORWARD0_9[25]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_9_SHFT      25
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_8_ADDR      BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_8_MASK      0x01000000                // BMC_STRAIGHTFORWARD0_8[24]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_8_SHFT      24
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_7_ADDR      BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_7_MASK      0x00800000                // BMC_STRAIGHTFORWARD0_7[23]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_7_SHFT      23
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_6_ADDR      BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_6_MASK      0x00400000                // BMC_STRAIGHTFORWARD0_6[22]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_6_SHFT      22
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_5_ADDR      BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_5_MASK      0x00200000                // BMC_STRAIGHTFORWARD0_5[21]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_5_SHFT      21
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_4_ADDR      BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_4_MASK      0x00100000                // BMC_STRAIGHTFORWARD0_4[20]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_4_SHFT      20
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_3_ADDR      BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_3_MASK      0x00080000                // BMC_STRAIGHTFORWARD0_3[19]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_3_SHFT      19
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_2_ADDR      BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_2_MASK      0x00040000                // BMC_STRAIGHTFORWARD0_2[18]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_2_SHFT      18
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_1_ADDR      BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_1_MASK      0x00020000                // BMC_STRAIGHTFORWARD0_1[17]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_1_SHFT      17
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD3_ADDR        BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD3_MASK        0x00000008                // BMC_STRAIGHTFORWARD3[3]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD3_SHFT        3
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD2_ADDR        BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD2_MASK        0x00000004                // BMC_STRAIGHTFORWARD2[2]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD2_SHFT        2
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD1_ADDR        BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD1_MASK        0x00000002                // BMC_STRAIGHTFORWARD1[1]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD1_SHFT        1
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_0_ADDR      BN0_WF_ARB_TOP_BMCCR6_ADDR
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_0_MASK      0x00000001                // BMC_STRAIGHTFORWARD0_0[0]
#define BN0_WF_ARB_TOP_BMCCR6_BMC_STRAIGHTFORWARD0_0_SHFT      0

/* =====================================================================================

  ---TXHANGTO (0x820E3000 + 0x0B8)---

    TX_HANG_TIME_OUT_LIMIT[17..0] - (RW) At the time resolution of 1us, when arb0/1_tx_active & ~agg0/1_arb_not_idle is true, ARB will increment count at each 1us. ARB will generate abort when the TX Hang Time Out Limit is reached.
    TX_HANG_TIMEOUT_EVENT_CNT0[24..18] - (RO) If TX_HANG_TIMEOUT_EN is 0, this value is 0.
                                     If TX_HANG_TIMEOUT_EN is 1, this value is incremented by 1 whenever the time length of arb0/1_tx_active being 1 continuously is equal to TX_HANG_TIMEOUT_LIMIT.
                                     Thus, SW can monitor this value to observe how often TX HANG TIMEOUT occurs.
    RESERVED25[31..25]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TXHANGTO_TX_HANG_TIMEOUT_EVENT_CNT0_ADDR BN0_WF_ARB_TOP_TXHANGTO_ADDR
#define BN0_WF_ARB_TOP_TXHANGTO_TX_HANG_TIMEOUT_EVENT_CNT0_MASK 0x01FC0000                // TX_HANG_TIMEOUT_EVENT_CNT0[24..18]
#define BN0_WF_ARB_TOP_TXHANGTO_TX_HANG_TIMEOUT_EVENT_CNT0_SHFT 18
#define BN0_WF_ARB_TOP_TXHANGTO_TX_HANG_TIME_OUT_LIMIT_ADDR    BN0_WF_ARB_TOP_TXHANGTO_ADDR
#define BN0_WF_ARB_TOP_TXHANGTO_TX_HANG_TIME_OUT_LIMIT_MASK    0x0003FFFF                // TX_HANG_TIME_OUT_LIMIT[17..0]
#define BN0_WF_ARB_TOP_TXHANGTO_TX_HANG_TIME_OUT_LIMIT_SHFT    0

/* =====================================================================================

  ---TQFAXM0 (0x820E3000 + 0x0C0)---

    TXCMD_TF0_FLUSH0[0]          - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TF0_FLUSH1[1]          - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TF0_FLUSH2[2]          - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TF0_FLUSH3[3]          - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TF0_FLUSH4[4]          - (W1S) Same as AC00_FLUSH0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    TXCMD_ALTX0_FLUSH0[8]        - (W1S) Same as AC00_FLUSH0~4
    TXCMD_ALTX0_FLUSH1[9]        - (W1S) Same as AC00_FLUSH0~4
    TXCMD_ALTX0_FLUSH2[10]       - (W1S) Same as AC00_FLUSH0~4
    TXCMD_ALTX0_FLUSH3[11]       - (W1S) Same as AC00_FLUSH0~4
    TXCMD_ALTX0_FLUSH4[12]       - (W1S) Same as AC00_FLUSH0~4
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH4_ADDR         BN0_WF_ARB_TOP_TQFAXM0_ADDR
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH4_MASK         0x00001000                // TXCMD_ALTX0_FLUSH4[12]
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH4_SHFT         12
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH3_ADDR         BN0_WF_ARB_TOP_TQFAXM0_ADDR
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH3_MASK         0x00000800                // TXCMD_ALTX0_FLUSH3[11]
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH3_SHFT         11
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH2_ADDR         BN0_WF_ARB_TOP_TQFAXM0_ADDR
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH2_MASK         0x00000400                // TXCMD_ALTX0_FLUSH2[10]
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH2_SHFT         10
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH1_ADDR         BN0_WF_ARB_TOP_TQFAXM0_ADDR
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH1_MASK         0x00000200                // TXCMD_ALTX0_FLUSH1[9]
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH1_SHFT         9
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH0_ADDR         BN0_WF_ARB_TOP_TQFAXM0_ADDR
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH0_MASK         0x00000100                // TXCMD_ALTX0_FLUSH0[8]
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_ALTX0_FLUSH0_SHFT         8
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH4_ADDR           BN0_WF_ARB_TOP_TQFAXM0_ADDR
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH4_MASK           0x00000010                // TXCMD_TF0_FLUSH4[4]
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH4_SHFT           4
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH3_ADDR           BN0_WF_ARB_TOP_TQFAXM0_ADDR
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH3_MASK           0x00000008                // TXCMD_TF0_FLUSH3[3]
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH3_SHFT           3
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH2_ADDR           BN0_WF_ARB_TOP_TQFAXM0_ADDR
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH2_MASK           0x00000004                // TXCMD_TF0_FLUSH2[2]
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH2_SHFT           2
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH1_ADDR           BN0_WF_ARB_TOP_TQFAXM0_ADDR
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH1_MASK           0x00000002                // TXCMD_TF0_FLUSH1[1]
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH1_SHFT           1
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH0_ADDR           BN0_WF_ARB_TOP_TQFAXM0_ADDR
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH0_MASK           0x00000001                // TXCMD_TF0_FLUSH0[0]
#define BN0_WF_ARB_TOP_TQFAXM0_TXCMD_TF0_FLUSH0_SHFT           0

/* =====================================================================================

  ---TQFTWT0 (0x820E3000 + 0x0C8)---

    TXCMD_TWTDL0_FLUSH0[0]       - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTDL0_FLUSH1[1]       - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTDL0_FLUSH2[2]       - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTDL0_FLUSH3[3]       - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTDL0_FLUSH4[4]       - (W1S) Same as AC00_FLUSH0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    TXCMD_TWTUL0_FLUSH0[8]       - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTUL0_FLUSH1[9]       - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTUL0_FLUSH2[10]      - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTUL0_FLUSH3[11]      - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTUL0_FLUSH4[12]      - (W1S) Same as AC00_FLUSH0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    TXCMD_TWTTSFTF0_FLUSH0[16]   - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTTSFTF0_FLUSH1[17]   - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTTSFTF0_FLUSH2[18]   - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTTSFTF0_FLUSH3[19]   - (W1S) Same as AC00_FLUSH0~4
    TXCMD_TWTTSFTF0_FLUSH4[20]   - (W1S) Same as AC00_FLUSH0~4
    RESERVED21[31..21]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH4_ADDR     BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH4_MASK     0x00100000                // TXCMD_TWTTSFTF0_FLUSH4[20]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH4_SHFT     20
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH3_ADDR     BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH3_MASK     0x00080000                // TXCMD_TWTTSFTF0_FLUSH3[19]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH3_SHFT     19
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH2_ADDR     BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH2_MASK     0x00040000                // TXCMD_TWTTSFTF0_FLUSH2[18]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH2_SHFT     18
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH1_ADDR     BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH1_MASK     0x00020000                // TXCMD_TWTTSFTF0_FLUSH1[17]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH1_SHFT     17
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH0_ADDR     BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH0_MASK     0x00010000                // TXCMD_TWTTSFTF0_FLUSH0[16]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTTSFTF0_FLUSH0_SHFT     16
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH4_ADDR        BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH4_MASK        0x00001000                // TXCMD_TWTUL0_FLUSH4[12]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH4_SHFT        12
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH3_ADDR        BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH3_MASK        0x00000800                // TXCMD_TWTUL0_FLUSH3[11]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH3_SHFT        11
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH2_ADDR        BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH2_MASK        0x00000400                // TXCMD_TWTUL0_FLUSH2[10]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH2_SHFT        10
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH1_ADDR        BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH1_MASK        0x00000200                // TXCMD_TWTUL0_FLUSH1[9]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH1_SHFT        9
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH0_ADDR        BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH0_MASK        0x00000100                // TXCMD_TWTUL0_FLUSH0[8]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTUL0_FLUSH0_SHFT        8
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH4_ADDR        BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH4_MASK        0x00000010                // TXCMD_TWTDL0_FLUSH4[4]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH4_SHFT        4
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH3_ADDR        BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH3_MASK        0x00000008                // TXCMD_TWTDL0_FLUSH3[3]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH3_SHFT        3
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH2_ADDR        BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH2_MASK        0x00000004                // TXCMD_TWTDL0_FLUSH2[2]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH2_SHFT        2
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH1_ADDR        BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH1_MASK        0x00000002                // TXCMD_TWTDL0_FLUSH1[1]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH1_SHFT        1
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH0_ADDR        BN0_WF_ARB_TOP_TQFTWT0_ADDR
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH0_MASK        0x00000001                // TXCMD_TWTDL0_FLUSH0[0]
#define BN0_WF_ARB_TOP_TQFTWT0_TXCMD_TWTDL0_FLUSH0_SHFT        0

/* =====================================================================================

  ---TQPAXM0 (0x820E3000 + 0x0D0)---

    TXCMD_TF0_PAUSE0[0]          - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TF0_PAUSE1[1]          - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TF0_PAUSE2[2]          - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TF0_PAUSE3[3]          - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TF0_PAUSE4[4]          - (W1S) Same as AC00_PAUSE0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    TXCMD_ALTX0_PAUSE0[8]        - (W1S) Same as AC00_PAUSE0~4
    TXCMD_ALTX0_PAUSE1[9]        - (W1S) Same as AC00_PAUSE0~4
    TXCMD_ALTX0_PAUSE2[10]       - (W1S) Same as AC00_PAUSE0~4
    TXCMD_ALTX0_PAUSE3[11]       - (W1S) Same as AC00_PAUSE0~4
    TXCMD_ALTX0_PAUSE4[12]       - (W1S) Same as AC00_PAUSE0~4
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE4_ADDR         BN0_WF_ARB_TOP_TQPAXM0_ADDR
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE4_MASK         0x00001000                // TXCMD_ALTX0_PAUSE4[12]
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE4_SHFT         12
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE3_ADDR         BN0_WF_ARB_TOP_TQPAXM0_ADDR
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE3_MASK         0x00000800                // TXCMD_ALTX0_PAUSE3[11]
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE3_SHFT         11
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE2_ADDR         BN0_WF_ARB_TOP_TQPAXM0_ADDR
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE2_MASK         0x00000400                // TXCMD_ALTX0_PAUSE2[10]
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE2_SHFT         10
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE1_ADDR         BN0_WF_ARB_TOP_TQPAXM0_ADDR
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE1_MASK         0x00000200                // TXCMD_ALTX0_PAUSE1[9]
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE1_SHFT         9
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE0_ADDR         BN0_WF_ARB_TOP_TQPAXM0_ADDR
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE0_MASK         0x00000100                // TXCMD_ALTX0_PAUSE0[8]
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_ALTX0_PAUSE0_SHFT         8
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE4_ADDR           BN0_WF_ARB_TOP_TQPAXM0_ADDR
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE4_MASK           0x00000010                // TXCMD_TF0_PAUSE4[4]
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE4_SHFT           4
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE3_ADDR           BN0_WF_ARB_TOP_TQPAXM0_ADDR
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE3_MASK           0x00000008                // TXCMD_TF0_PAUSE3[3]
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE3_SHFT           3
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE2_ADDR           BN0_WF_ARB_TOP_TQPAXM0_ADDR
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE2_MASK           0x00000004                // TXCMD_TF0_PAUSE2[2]
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE2_SHFT           2
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE1_ADDR           BN0_WF_ARB_TOP_TQPAXM0_ADDR
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE1_MASK           0x00000002                // TXCMD_TF0_PAUSE1[1]
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE1_SHFT           1
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE0_ADDR           BN0_WF_ARB_TOP_TQPAXM0_ADDR
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE0_MASK           0x00000001                // TXCMD_TF0_PAUSE0[0]
#define BN0_WF_ARB_TOP_TQPAXM0_TXCMD_TF0_PAUSE0_SHFT           0

/* =====================================================================================

  ---TQPTWT0 (0x820E3000 + 0x0D8)---

    TXCMD_TWTDL0_PAUSE0[0]       - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTDL0_PAUSE1[1]       - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTDL0_PAUSE2[2]       - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTDL0_PAUSE3[3]       - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTDL0_PAUSE4[4]       - (W1S) Same as AC00_PAUSE0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    TXCMD_TWTUL0_PAUSE0[8]       - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTUL0_PAUSE1[9]       - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTUL0_PAUSE2[10]      - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTUL0_PAUSE3[11]      - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTUL0_PAUSE4[12]      - (W1S) Same as AC00_PAUSE0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    TXCMD_TWTTSFTF0_PAUSE0[16]   - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTTSFTF0_PAUSE1[17]   - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTTSFTF0_PAUSE2[18]   - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTTSFTF0_PAUSE3[19]   - (W1S) Same as AC00_PAUSE0~4
    TXCMD_TWTTSFTF0_PAUSE4[20]   - (W1S) Same as AC00_PAUSE0~4
    RESERVED21[31..21]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE4_ADDR     BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE4_MASK     0x00100000                // TXCMD_TWTTSFTF0_PAUSE4[20]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE4_SHFT     20
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE3_ADDR     BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE3_MASK     0x00080000                // TXCMD_TWTTSFTF0_PAUSE3[19]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE3_SHFT     19
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE2_ADDR     BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE2_MASK     0x00040000                // TXCMD_TWTTSFTF0_PAUSE2[18]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE2_SHFT     18
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE1_ADDR     BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE1_MASK     0x00020000                // TXCMD_TWTTSFTF0_PAUSE1[17]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE1_SHFT     17
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE0_ADDR     BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE0_MASK     0x00010000                // TXCMD_TWTTSFTF0_PAUSE0[16]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTTSFTF0_PAUSE0_SHFT     16
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE4_ADDR        BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE4_MASK        0x00001000                // TXCMD_TWTUL0_PAUSE4[12]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE4_SHFT        12
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE3_ADDR        BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE3_MASK        0x00000800                // TXCMD_TWTUL0_PAUSE3[11]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE3_SHFT        11
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE2_ADDR        BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE2_MASK        0x00000400                // TXCMD_TWTUL0_PAUSE2[10]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE2_SHFT        10
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE1_ADDR        BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE1_MASK        0x00000200                // TXCMD_TWTUL0_PAUSE1[9]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE1_SHFT        9
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE0_ADDR        BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE0_MASK        0x00000100                // TXCMD_TWTUL0_PAUSE0[8]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTUL0_PAUSE0_SHFT        8
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE4_ADDR        BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE4_MASK        0x00000010                // TXCMD_TWTDL0_PAUSE4[4]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE4_SHFT        4
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE3_ADDR        BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE3_MASK        0x00000008                // TXCMD_TWTDL0_PAUSE3[3]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE3_SHFT        3
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE2_ADDR        BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE2_MASK        0x00000004                // TXCMD_TWTDL0_PAUSE2[2]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE2_SHFT        2
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE1_ADDR        BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE1_MASK        0x00000002                // TXCMD_TWTDL0_PAUSE1[1]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE1_SHFT        1
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE0_ADDR        BN0_WF_ARB_TOP_TQPTWT0_ADDR
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE0_MASK        0x00000001                // TXCMD_TWTDL0_PAUSE0[0]
#define BN0_WF_ARB_TOP_TQPTWT0_TXCMD_TWTDL0_PAUSE0_SHFT        0

/* =====================================================================================

  ---GTQR6 (0x820E3000 + 0x0E0)---

    GUARD_TIME_TXCMD_TF0[7..0]   - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_TXCMD_ALTX0[15..8] - (RW) The same as GUARD_TIME_AC00.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_GTQR6_GUARD_TIME_TXCMD_ALTX0_ADDR       BN0_WF_ARB_TOP_GTQR6_ADDR
#define BN0_WF_ARB_TOP_GTQR6_GUARD_TIME_TXCMD_ALTX0_MASK       0x0000FF00                // GUARD_TIME_TXCMD_ALTX0[15..8]
#define BN0_WF_ARB_TOP_GTQR6_GUARD_TIME_TXCMD_ALTX0_SHFT       8
#define BN0_WF_ARB_TOP_GTQR6_GUARD_TIME_TXCMD_TF0_ADDR         BN0_WF_ARB_TOP_GTQR6_ADDR
#define BN0_WF_ARB_TOP_GTQR6_GUARD_TIME_TXCMD_TF0_MASK         0x000000FF                // GUARD_TIME_TXCMD_TF0[7..0]
#define BN0_WF_ARB_TOP_GTQR6_GUARD_TIME_TXCMD_TF0_SHFT         0

/* =====================================================================================

  ---GTQR8 (0x820E3000 + 0x0E8)---

    GUARD_TIME_TXCMD_TWT_DL0[7..0] - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_TXCMD_TWT_UL0[15..8] - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_TXCMD_TWT_TSF_TF0[23..16] - (RW) The same as GUARD_TIME_AC00.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_GTQR8_GUARD_TIME_TXCMD_TWT_TSF_TF0_ADDR BN0_WF_ARB_TOP_GTQR8_ADDR
#define BN0_WF_ARB_TOP_GTQR8_GUARD_TIME_TXCMD_TWT_TSF_TF0_MASK 0x00FF0000                // GUARD_TIME_TXCMD_TWT_TSF_TF0[23..16]
#define BN0_WF_ARB_TOP_GTQR8_GUARD_TIME_TXCMD_TWT_TSF_TF0_SHFT 16
#define BN0_WF_ARB_TOP_GTQR8_GUARD_TIME_TXCMD_TWT_UL0_ADDR     BN0_WF_ARB_TOP_GTQR8_ADDR
#define BN0_WF_ARB_TOP_GTQR8_GUARD_TIME_TXCMD_TWT_UL0_MASK     0x0000FF00                // GUARD_TIME_TXCMD_TWT_UL0[15..8]
#define BN0_WF_ARB_TOP_GTQR8_GUARD_TIME_TXCMD_TWT_UL0_SHFT     8
#define BN0_WF_ARB_TOP_GTQR8_GUARD_TIME_TXCMD_TWT_DL0_ADDR     BN0_WF_ARB_TOP_GTQR8_ADDR
#define BN0_WF_ARB_TOP_GTQR8_GUARD_TIME_TXCMD_TWT_DL0_MASK     0x000000FF                // GUARD_TIME_TXCMD_TWT_DL0[7..0]
#define BN0_WF_ARB_TOP_GTQR8_GUARD_TIME_TXCMD_TWT_DL0_SHFT     0

/* =====================================================================================

  ---RSVD0 (0x820E3000 + 0x0F0)---

    RESERVED_0[31..0]            - (RW) This is reserved for potential ECO.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_RSVD0_RESERVED_0_ADDR                   BN0_WF_ARB_TOP_RSVD0_ADDR
#define BN0_WF_ARB_TOP_RSVD0_RESERVED_0_MASK                   0xFFFFFFFF                // RESERVED_0[31..0]
#define BN0_WF_ARB_TOP_RSVD0_RESERVED_0_SHFT                   0

/* =====================================================================================

  ---RSVD1 (0x820E3000 + 0x0F4)---

    PSOFF_REISSUE_RWP_INC[0]     - (RW) To solve PSOFF reissue problem
    WITHIN_TXOP_RESTART_PPDU_SREQ_THEN_CANCEL[1] - (RW) To solve TX Hang
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_RSVD1_WITHIN_TXOP_RESTART_PPDU_SREQ_THEN_CANCEL_ADDR BN0_WF_ARB_TOP_RSVD1_ADDR
#define BN0_WF_ARB_TOP_RSVD1_WITHIN_TXOP_RESTART_PPDU_SREQ_THEN_CANCEL_MASK 0x00000002                // WITHIN_TXOP_RESTART_PPDU_SREQ_THEN_CANCEL[1]
#define BN0_WF_ARB_TOP_RSVD1_WITHIN_TXOP_RESTART_PPDU_SREQ_THEN_CANCEL_SHFT 1
#define BN0_WF_ARB_TOP_RSVD1_PSOFF_REISSUE_RWP_INC_ADDR        BN0_WF_ARB_TOP_RSVD1_ADDR
#define BN0_WF_ARB_TOP_RSVD1_PSOFF_REISSUE_RWP_INC_MASK        0x00000001                // PSOFF_REISSUE_RWP_INC[0]
#define BN0_WF_ARB_TOP_RSVD1_PSOFF_REISSUE_RWP_INC_SHFT        0

/* =====================================================================================

  ---RSVD (0x820E3000 + 0x0FC)---

    BMC_DROP_EN[0]               - (RW) Broadcast drop sync. to BMC_CNT* enable. The drop may be life timeout or retry limit
                                     (ECO backup sulotion)
                                       0: the BMC_CNT* will not decrease (this is a HW bug)
                                       1: the BMC_CNT* will decrease
    NBCN_DROP_EN[1]              - (RW) NAN Beacon active will freeze other queue. When NBCN drop release to other queue or not.
                                       0: don't release to other queue when NBCN drop
                                       1: release to other queue when NBCN drop
    BF_WAIT_AGG_IDLE[2]          - (RW) This enables the generation of arb0/1_tx_end to pull down the arb0/1_tx_active only after AGG becomes idle.
    AGG_BUSY_FREEZE_BF[3]        - (RW) This enables the all_freeze0/1_flag == 1 when AGG is still busy to freeze all back-off engines.
    PTA_RWP_1WEX_LP1USTICK_D[4]  - (RW) This solves a bug for 1-Wire-Extend feature. When this is enabled, the lp_1us_tick signal is delayed 1 clock to generate the necessary pulse to further generate rw_win_inc/dec to then further generate rw_enter_protect and rw_exit_protect. Without it, 1-Wire-Extend mostly won't work.
    TX_ACTIVE_HANG_WATCHDOG_TIMER[5] - (RW) If set to 1, arb0/1_tx_active is added to arb0/1_not_idle.
    OTHERS_HANG_WATCHDOG_TIMER[6] - (RW) If set to 1, min0/1_busy, umac0/1_busy, arb_mu_req, and arb0/1_agg_active are added to arb0/1_not_idle.
    TX_HANG_TIMEOUT_EN[7]        - (RW) If set to 1, the time length of arb0/1_tx_active being 1 will be continuously incremented at each 32us and compared against TX_HANG_TIMEOUT_LIMIT.
    ABORT_SLOT_FIX_DIS[8]        - (RW) The bug, abort and slot idle at the same T, fix or not
                                     0: fix bug
                                     1: legacy design (exist bug)
    RESERVED9[9]                 - (RO) Reserved bits
    RESERVED[31..10]             - (RW) This is reserved for potential ECO.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_RSVD_ABORT_SLOT_FIX_DIS_ADDR            BN0_WF_ARB_TOP_RSVD_ADDR
#define BN0_WF_ARB_TOP_RSVD_ABORT_SLOT_FIX_DIS_MASK            0x00000100                // ABORT_SLOT_FIX_DIS[8]
#define BN0_WF_ARB_TOP_RSVD_ABORT_SLOT_FIX_DIS_SHFT            8
#define BN0_WF_ARB_TOP_RSVD_TX_HANG_TIMEOUT_EN_ADDR            BN0_WF_ARB_TOP_RSVD_ADDR
#define BN0_WF_ARB_TOP_RSVD_TX_HANG_TIMEOUT_EN_MASK            0x00000080                // TX_HANG_TIMEOUT_EN[7]
#define BN0_WF_ARB_TOP_RSVD_TX_HANG_TIMEOUT_EN_SHFT            7
#define BN0_WF_ARB_TOP_RSVD_OTHERS_HANG_WATCHDOG_TIMER_ADDR    BN0_WF_ARB_TOP_RSVD_ADDR
#define BN0_WF_ARB_TOP_RSVD_OTHERS_HANG_WATCHDOG_TIMER_MASK    0x00000040                // OTHERS_HANG_WATCHDOG_TIMER[6]
#define BN0_WF_ARB_TOP_RSVD_OTHERS_HANG_WATCHDOG_TIMER_SHFT    6
#define BN0_WF_ARB_TOP_RSVD_TX_ACTIVE_HANG_WATCHDOG_TIMER_ADDR BN0_WF_ARB_TOP_RSVD_ADDR
#define BN0_WF_ARB_TOP_RSVD_TX_ACTIVE_HANG_WATCHDOG_TIMER_MASK 0x00000020                // TX_ACTIVE_HANG_WATCHDOG_TIMER[5]
#define BN0_WF_ARB_TOP_RSVD_TX_ACTIVE_HANG_WATCHDOG_TIMER_SHFT 5
#define BN0_WF_ARB_TOP_RSVD_PTA_RWP_1WEX_LP1USTICK_D_ADDR      BN0_WF_ARB_TOP_RSVD_ADDR
#define BN0_WF_ARB_TOP_RSVD_PTA_RWP_1WEX_LP1USTICK_D_MASK      0x00000010                // PTA_RWP_1WEX_LP1USTICK_D[4]
#define BN0_WF_ARB_TOP_RSVD_PTA_RWP_1WEX_LP1USTICK_D_SHFT      4
#define BN0_WF_ARB_TOP_RSVD_AGG_BUSY_FREEZE_BF_ADDR            BN0_WF_ARB_TOP_RSVD_ADDR
#define BN0_WF_ARB_TOP_RSVD_AGG_BUSY_FREEZE_BF_MASK            0x00000008                // AGG_BUSY_FREEZE_BF[3]
#define BN0_WF_ARB_TOP_RSVD_AGG_BUSY_FREEZE_BF_SHFT            3
#define BN0_WF_ARB_TOP_RSVD_BF_WAIT_AGG_IDLE_ADDR              BN0_WF_ARB_TOP_RSVD_ADDR
#define BN0_WF_ARB_TOP_RSVD_BF_WAIT_AGG_IDLE_MASK              0x00000004                // BF_WAIT_AGG_IDLE[2]
#define BN0_WF_ARB_TOP_RSVD_BF_WAIT_AGG_IDLE_SHFT              2
#define BN0_WF_ARB_TOP_RSVD_NBCN_DROP_EN_ADDR                  BN0_WF_ARB_TOP_RSVD_ADDR
#define BN0_WF_ARB_TOP_RSVD_NBCN_DROP_EN_MASK                  0x00000002                // NBCN_DROP_EN[1]
#define BN0_WF_ARB_TOP_RSVD_NBCN_DROP_EN_SHFT                  1
#define BN0_WF_ARB_TOP_RSVD_BMC_DROP_EN_ADDR                   BN0_WF_ARB_TOP_RSVD_ADDR
#define BN0_WF_ARB_TOP_RSVD_BMC_DROP_EN_MASK                   0x00000001                // BMC_DROP_EN[0]
#define BN0_WF_ARB_TOP_RSVD_BMC_DROP_EN_SHFT                   0

/* =====================================================================================

  ---TQSW0 (0x820E3000 + 0x100)---

    AC00_START0[0]               - (W1S) Start the AC00 BSSID0 Queue to operate.  The LMAC start the transmission.
                                     Firmware writes 1 to enable. Write 0 is meaningless.
                                     Read returns the AC0 BSSID0 enable or not.
                                     Once stop or flush or trap happened, FW should set START again to enable the queue.
    AC00_START1[1]               - (W1S) Start the AC00 BSSID1 Queue to operate.
                                     Same as AC00_START0
    AC00_START2[2]               - (W1S) Start the AC00 BSSID2 Queue to operate.
                                     Same as AC00_START0
    AC00_START3[3]               - (W1S) Start the AC00 BSSID3 Queue to operate.
                                     Same as AC00_START0
    AC00_START4[4]               - (W1S) Start the AC00 BSSID4 Queue to operate.
                                     Same as AC00_START0
    RESERVED5[7..5]              - (RO) Reserved bits
    AC01_START0[8]               - (W1S) Same as AC00_START0~4
    AC01_START1[9]               - (W1S) Same as AC00_START0~4
    AC01_START2[10]              - (W1S) Same as AC00_START0~4
    AC01_START3[11]              - (W1S) Same as AC00_START0~4
    AC01_START4[12]              - (W1S) Same as AC00_START0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC02_START0[16]              - (W1S) Same as AC00_START0~4
    AC02_START1[17]              - (W1S) Same as AC00_START0~4
    AC02_START2[18]              - (W1S) Same as AC00_START0~4
    AC02_START3[19]              - (W1S) Same as AC00_START0~4
    AC02_START4[20]              - (W1S) Same as AC00_START0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC03_START0[24]              - (W1S) Same as AC00_START0~4
    AC03_START1[25]              - (W1S) Same as AC00_START0~4
    AC03_START2[26]              - (W1S) Same as AC00_START0~4
    AC03_START3[27]              - (W1S) Same as AC00_START0~4
    AC03_START4[28]              - (W1S) Same as AC00_START0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQSW0_AC03_START4_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC03_START4_MASK                  0x10000000                // AC03_START4[28]
#define BN0_WF_ARB_TOP_TQSW0_AC03_START4_SHFT                  28
#define BN0_WF_ARB_TOP_TQSW0_AC03_START3_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC03_START3_MASK                  0x08000000                // AC03_START3[27]
#define BN0_WF_ARB_TOP_TQSW0_AC03_START3_SHFT                  27
#define BN0_WF_ARB_TOP_TQSW0_AC03_START2_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC03_START2_MASK                  0x04000000                // AC03_START2[26]
#define BN0_WF_ARB_TOP_TQSW0_AC03_START2_SHFT                  26
#define BN0_WF_ARB_TOP_TQSW0_AC03_START1_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC03_START1_MASK                  0x02000000                // AC03_START1[25]
#define BN0_WF_ARB_TOP_TQSW0_AC03_START1_SHFT                  25
#define BN0_WF_ARB_TOP_TQSW0_AC03_START0_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC03_START0_MASK                  0x01000000                // AC03_START0[24]
#define BN0_WF_ARB_TOP_TQSW0_AC03_START0_SHFT                  24
#define BN0_WF_ARB_TOP_TQSW0_AC02_START4_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC02_START4_MASK                  0x00100000                // AC02_START4[20]
#define BN0_WF_ARB_TOP_TQSW0_AC02_START4_SHFT                  20
#define BN0_WF_ARB_TOP_TQSW0_AC02_START3_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC02_START3_MASK                  0x00080000                // AC02_START3[19]
#define BN0_WF_ARB_TOP_TQSW0_AC02_START3_SHFT                  19
#define BN0_WF_ARB_TOP_TQSW0_AC02_START2_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC02_START2_MASK                  0x00040000                // AC02_START2[18]
#define BN0_WF_ARB_TOP_TQSW0_AC02_START2_SHFT                  18
#define BN0_WF_ARB_TOP_TQSW0_AC02_START1_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC02_START1_MASK                  0x00020000                // AC02_START1[17]
#define BN0_WF_ARB_TOP_TQSW0_AC02_START1_SHFT                  17
#define BN0_WF_ARB_TOP_TQSW0_AC02_START0_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC02_START0_MASK                  0x00010000                // AC02_START0[16]
#define BN0_WF_ARB_TOP_TQSW0_AC02_START0_SHFT                  16
#define BN0_WF_ARB_TOP_TQSW0_AC01_START4_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC01_START4_MASK                  0x00001000                // AC01_START4[12]
#define BN0_WF_ARB_TOP_TQSW0_AC01_START4_SHFT                  12
#define BN0_WF_ARB_TOP_TQSW0_AC01_START3_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC01_START3_MASK                  0x00000800                // AC01_START3[11]
#define BN0_WF_ARB_TOP_TQSW0_AC01_START3_SHFT                  11
#define BN0_WF_ARB_TOP_TQSW0_AC01_START2_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC01_START2_MASK                  0x00000400                // AC01_START2[10]
#define BN0_WF_ARB_TOP_TQSW0_AC01_START2_SHFT                  10
#define BN0_WF_ARB_TOP_TQSW0_AC01_START1_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC01_START1_MASK                  0x00000200                // AC01_START1[9]
#define BN0_WF_ARB_TOP_TQSW0_AC01_START1_SHFT                  9
#define BN0_WF_ARB_TOP_TQSW0_AC01_START0_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC01_START0_MASK                  0x00000100                // AC01_START0[8]
#define BN0_WF_ARB_TOP_TQSW0_AC01_START0_SHFT                  8
#define BN0_WF_ARB_TOP_TQSW0_AC00_START4_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC00_START4_MASK                  0x00000010                // AC00_START4[4]
#define BN0_WF_ARB_TOP_TQSW0_AC00_START4_SHFT                  4
#define BN0_WF_ARB_TOP_TQSW0_AC00_START3_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC00_START3_MASK                  0x00000008                // AC00_START3[3]
#define BN0_WF_ARB_TOP_TQSW0_AC00_START3_SHFT                  3
#define BN0_WF_ARB_TOP_TQSW0_AC00_START2_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC00_START2_MASK                  0x00000004                // AC00_START2[2]
#define BN0_WF_ARB_TOP_TQSW0_AC00_START2_SHFT                  2
#define BN0_WF_ARB_TOP_TQSW0_AC00_START1_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC00_START1_MASK                  0x00000002                // AC00_START1[1]
#define BN0_WF_ARB_TOP_TQSW0_AC00_START1_SHFT                  1
#define BN0_WF_ARB_TOP_TQSW0_AC00_START0_ADDR                  BN0_WF_ARB_TOP_TQSW0_ADDR
#define BN0_WF_ARB_TOP_TQSW0_AC00_START0_MASK                  0x00000001                // AC00_START0[0]
#define BN0_WF_ARB_TOP_TQSW0_AC00_START0_SHFT                  0

/* =====================================================================================

  ---TQSW1 (0x820E3000 + 0x104)---

    AC10_START0[0]               - (W1S) Same as AC00_START0~4
    AC10_START1[1]               - (W1S) Same as AC00_START0~4
    AC10_START2[2]               - (W1S) Same as AC00_START0~4
    AC10_START3[3]               - (W1S) Same as AC00_START0~4
    AC10_START4[4]               - (W1S) Same as AC00_START0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    AC11_START0[8]               - (W1S) Same as AC00_START0~4
    AC11_START1[9]               - (W1S) Same as AC00_START0~4
    AC11_START2[10]              - (W1S) Same as AC00_START0~4
    AC11_START3[11]              - (W1S) Same as AC00_START0~4
    AC11_START4[12]              - (W1S) Same as AC00_START0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC12_START0[16]              - (W1S) Same as AC00_START0~4
    AC12_START1[17]              - (W1S) Same as AC00_START0~4
    AC12_START2[18]              - (W1S) Same as AC00_START0~4
    AC12_START3[19]              - (W1S) Same as AC00_START0~4
    AC12_START4[20]              - (W1S) Same as AC00_START0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC13_START0[24]              - (W1S) Same as AC00_START0~4
    AC13_START1[25]              - (W1S) Same as AC00_START0~4
    AC13_START2[26]              - (W1S) Same as AC00_START0~4
    AC13_START3[27]              - (W1S) Same as AC00_START0~4
    AC13_START4[28]              - (W1S) Same as AC00_START0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQSW1_AC13_START4_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC13_START4_MASK                  0x10000000                // AC13_START4[28]
#define BN0_WF_ARB_TOP_TQSW1_AC13_START4_SHFT                  28
#define BN0_WF_ARB_TOP_TQSW1_AC13_START3_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC13_START3_MASK                  0x08000000                // AC13_START3[27]
#define BN0_WF_ARB_TOP_TQSW1_AC13_START3_SHFT                  27
#define BN0_WF_ARB_TOP_TQSW1_AC13_START2_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC13_START2_MASK                  0x04000000                // AC13_START2[26]
#define BN0_WF_ARB_TOP_TQSW1_AC13_START2_SHFT                  26
#define BN0_WF_ARB_TOP_TQSW1_AC13_START1_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC13_START1_MASK                  0x02000000                // AC13_START1[25]
#define BN0_WF_ARB_TOP_TQSW1_AC13_START1_SHFT                  25
#define BN0_WF_ARB_TOP_TQSW1_AC13_START0_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC13_START0_MASK                  0x01000000                // AC13_START0[24]
#define BN0_WF_ARB_TOP_TQSW1_AC13_START0_SHFT                  24
#define BN0_WF_ARB_TOP_TQSW1_AC12_START4_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC12_START4_MASK                  0x00100000                // AC12_START4[20]
#define BN0_WF_ARB_TOP_TQSW1_AC12_START4_SHFT                  20
#define BN0_WF_ARB_TOP_TQSW1_AC12_START3_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC12_START3_MASK                  0x00080000                // AC12_START3[19]
#define BN0_WF_ARB_TOP_TQSW1_AC12_START3_SHFT                  19
#define BN0_WF_ARB_TOP_TQSW1_AC12_START2_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC12_START2_MASK                  0x00040000                // AC12_START2[18]
#define BN0_WF_ARB_TOP_TQSW1_AC12_START2_SHFT                  18
#define BN0_WF_ARB_TOP_TQSW1_AC12_START1_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC12_START1_MASK                  0x00020000                // AC12_START1[17]
#define BN0_WF_ARB_TOP_TQSW1_AC12_START1_SHFT                  17
#define BN0_WF_ARB_TOP_TQSW1_AC12_START0_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC12_START0_MASK                  0x00010000                // AC12_START0[16]
#define BN0_WF_ARB_TOP_TQSW1_AC12_START0_SHFT                  16
#define BN0_WF_ARB_TOP_TQSW1_AC11_START4_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC11_START4_MASK                  0x00001000                // AC11_START4[12]
#define BN0_WF_ARB_TOP_TQSW1_AC11_START4_SHFT                  12
#define BN0_WF_ARB_TOP_TQSW1_AC11_START3_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC11_START3_MASK                  0x00000800                // AC11_START3[11]
#define BN0_WF_ARB_TOP_TQSW1_AC11_START3_SHFT                  11
#define BN0_WF_ARB_TOP_TQSW1_AC11_START2_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC11_START2_MASK                  0x00000400                // AC11_START2[10]
#define BN0_WF_ARB_TOP_TQSW1_AC11_START2_SHFT                  10
#define BN0_WF_ARB_TOP_TQSW1_AC11_START1_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC11_START1_MASK                  0x00000200                // AC11_START1[9]
#define BN0_WF_ARB_TOP_TQSW1_AC11_START1_SHFT                  9
#define BN0_WF_ARB_TOP_TQSW1_AC11_START0_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC11_START0_MASK                  0x00000100                // AC11_START0[8]
#define BN0_WF_ARB_TOP_TQSW1_AC11_START0_SHFT                  8
#define BN0_WF_ARB_TOP_TQSW1_AC10_START4_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC10_START4_MASK                  0x00000010                // AC10_START4[4]
#define BN0_WF_ARB_TOP_TQSW1_AC10_START4_SHFT                  4
#define BN0_WF_ARB_TOP_TQSW1_AC10_START3_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC10_START3_MASK                  0x00000008                // AC10_START3[3]
#define BN0_WF_ARB_TOP_TQSW1_AC10_START3_SHFT                  3
#define BN0_WF_ARB_TOP_TQSW1_AC10_START2_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC10_START2_MASK                  0x00000004                // AC10_START2[2]
#define BN0_WF_ARB_TOP_TQSW1_AC10_START2_SHFT                  2
#define BN0_WF_ARB_TOP_TQSW1_AC10_START1_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC10_START1_MASK                  0x00000002                // AC10_START1[1]
#define BN0_WF_ARB_TOP_TQSW1_AC10_START1_SHFT                  1
#define BN0_WF_ARB_TOP_TQSW1_AC10_START0_ADDR                  BN0_WF_ARB_TOP_TQSW1_ADDR
#define BN0_WF_ARB_TOP_TQSW1_AC10_START0_MASK                  0x00000001                // AC10_START0[0]
#define BN0_WF_ARB_TOP_TQSW1_AC10_START0_SHFT                  0

/* =====================================================================================

  ---TQSW2 (0x820E3000 + 0x108)---

    AC20_START0[0]               - (W1S) Same as AC00_START0~4
    AC20_START1[1]               - (W1S) Same as AC00_START0~4
    AC20_START2[2]               - (W1S) Same as AC00_START0~4
    AC20_START3[3]               - (W1S) Same as AC00_START0~4
    AC20_START4[4]               - (W1S) Same as AC00_START0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    AC21_START0[8]               - (W1S) Same as AC00_START0~4
    AC21_START1[9]               - (W1S) Same as AC00_START0~4
    AC21_START2[10]              - (W1S) Same as AC00_START0~4
    AC21_START3[11]              - (W1S) Same as AC00_START0~4
    AC21_START4[12]              - (W1S) Same as AC00_START0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC22_START0[16]              - (W1S) Same as AC00_START0~4
    AC22_START1[17]              - (W1S) Same as AC00_START0~4
    AC22_START2[18]              - (W1S) Same as AC00_START0~4
    AC22_START3[19]              - (W1S) Same as AC00_START0~4
    AC22_START4[20]              - (W1S) Same as AC00_START0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC23_START0[24]              - (W1S) Same as AC00_START0~4
    AC23_START1[25]              - (W1S) Same as AC00_START0~4
    AC23_START2[26]              - (W1S) Same as AC00_START0~4
    AC23_START3[27]              - (W1S) Same as AC00_START0~4
    AC23_START4[28]              - (W1S) Same as AC00_START0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQSW2_AC23_START4_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC23_START4_MASK                  0x10000000                // AC23_START4[28]
#define BN0_WF_ARB_TOP_TQSW2_AC23_START4_SHFT                  28
#define BN0_WF_ARB_TOP_TQSW2_AC23_START3_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC23_START3_MASK                  0x08000000                // AC23_START3[27]
#define BN0_WF_ARB_TOP_TQSW2_AC23_START3_SHFT                  27
#define BN0_WF_ARB_TOP_TQSW2_AC23_START2_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC23_START2_MASK                  0x04000000                // AC23_START2[26]
#define BN0_WF_ARB_TOP_TQSW2_AC23_START2_SHFT                  26
#define BN0_WF_ARB_TOP_TQSW2_AC23_START1_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC23_START1_MASK                  0x02000000                // AC23_START1[25]
#define BN0_WF_ARB_TOP_TQSW2_AC23_START1_SHFT                  25
#define BN0_WF_ARB_TOP_TQSW2_AC23_START0_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC23_START0_MASK                  0x01000000                // AC23_START0[24]
#define BN0_WF_ARB_TOP_TQSW2_AC23_START0_SHFT                  24
#define BN0_WF_ARB_TOP_TQSW2_AC22_START4_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC22_START4_MASK                  0x00100000                // AC22_START4[20]
#define BN0_WF_ARB_TOP_TQSW2_AC22_START4_SHFT                  20
#define BN0_WF_ARB_TOP_TQSW2_AC22_START3_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC22_START3_MASK                  0x00080000                // AC22_START3[19]
#define BN0_WF_ARB_TOP_TQSW2_AC22_START3_SHFT                  19
#define BN0_WF_ARB_TOP_TQSW2_AC22_START2_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC22_START2_MASK                  0x00040000                // AC22_START2[18]
#define BN0_WF_ARB_TOP_TQSW2_AC22_START2_SHFT                  18
#define BN0_WF_ARB_TOP_TQSW2_AC22_START1_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC22_START1_MASK                  0x00020000                // AC22_START1[17]
#define BN0_WF_ARB_TOP_TQSW2_AC22_START1_SHFT                  17
#define BN0_WF_ARB_TOP_TQSW2_AC22_START0_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC22_START0_MASK                  0x00010000                // AC22_START0[16]
#define BN0_WF_ARB_TOP_TQSW2_AC22_START0_SHFT                  16
#define BN0_WF_ARB_TOP_TQSW2_AC21_START4_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC21_START4_MASK                  0x00001000                // AC21_START4[12]
#define BN0_WF_ARB_TOP_TQSW2_AC21_START4_SHFT                  12
#define BN0_WF_ARB_TOP_TQSW2_AC21_START3_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC21_START3_MASK                  0x00000800                // AC21_START3[11]
#define BN0_WF_ARB_TOP_TQSW2_AC21_START3_SHFT                  11
#define BN0_WF_ARB_TOP_TQSW2_AC21_START2_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC21_START2_MASK                  0x00000400                // AC21_START2[10]
#define BN0_WF_ARB_TOP_TQSW2_AC21_START2_SHFT                  10
#define BN0_WF_ARB_TOP_TQSW2_AC21_START1_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC21_START1_MASK                  0x00000200                // AC21_START1[9]
#define BN0_WF_ARB_TOP_TQSW2_AC21_START1_SHFT                  9
#define BN0_WF_ARB_TOP_TQSW2_AC21_START0_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC21_START0_MASK                  0x00000100                // AC21_START0[8]
#define BN0_WF_ARB_TOP_TQSW2_AC21_START0_SHFT                  8
#define BN0_WF_ARB_TOP_TQSW2_AC20_START4_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC20_START4_MASK                  0x00000010                // AC20_START4[4]
#define BN0_WF_ARB_TOP_TQSW2_AC20_START4_SHFT                  4
#define BN0_WF_ARB_TOP_TQSW2_AC20_START3_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC20_START3_MASK                  0x00000008                // AC20_START3[3]
#define BN0_WF_ARB_TOP_TQSW2_AC20_START3_SHFT                  3
#define BN0_WF_ARB_TOP_TQSW2_AC20_START2_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC20_START2_MASK                  0x00000004                // AC20_START2[2]
#define BN0_WF_ARB_TOP_TQSW2_AC20_START2_SHFT                  2
#define BN0_WF_ARB_TOP_TQSW2_AC20_START1_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC20_START1_MASK                  0x00000002                // AC20_START1[1]
#define BN0_WF_ARB_TOP_TQSW2_AC20_START1_SHFT                  1
#define BN0_WF_ARB_TOP_TQSW2_AC20_START0_ADDR                  BN0_WF_ARB_TOP_TQSW2_ADDR
#define BN0_WF_ARB_TOP_TQSW2_AC20_START0_MASK                  0x00000001                // AC20_START0[0]
#define BN0_WF_ARB_TOP_TQSW2_AC20_START0_SHFT                  0

/* =====================================================================================

  ---TQSW3 (0x820E3000 + 0x10C)---

    AC30_START0[0]               - (W1S) Same as AC00_START0~4
    AC30_START1[1]               - (W1S) Same as AC00_START0~4
    AC30_START2[2]               - (W1S) Same as AC00_START0~4
    AC30_START3[3]               - (W1S) Same as AC00_START0~4
    AC30_START4[4]               - (W1S) Same as AC00_START0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    AC31_START0[8]               - (W1S) Same as AC00_START0~4
    AC31_START1[9]               - (W1S) Same as AC00_START0~4
    AC31_START2[10]              - (W1S) Same as AC00_START0~4
    AC31_START3[11]              - (W1S) Same as AC00_START0~4
    AC31_START4[12]              - (W1S) Same as AC00_START0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC32_START0[16]              - (W1S) Same as AC00_START0~4
    AC32_START1[17]              - (W1S) Same as AC00_START0~4
    AC32_START2[18]              - (W1S) Same as AC00_START0~4
    AC32_START3[19]              - (W1S) Same as AC00_START0~4
    AC32_START4[20]              - (W1S) Same as AC00_START0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC33_START0[24]              - (W1S) Same as AC00_START0~4
    AC33_START1[25]              - (W1S) Same as AC00_START0~4
    AC33_START2[26]              - (W1S) Same as AC00_START0~4
    AC33_START3[27]              - (W1S) Same as AC00_START0~4
    AC33_START4[28]              - (W1S) Same as AC00_START0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQSW3_AC33_START4_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC33_START4_MASK                  0x10000000                // AC33_START4[28]
#define BN0_WF_ARB_TOP_TQSW3_AC33_START4_SHFT                  28
#define BN0_WF_ARB_TOP_TQSW3_AC33_START3_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC33_START3_MASK                  0x08000000                // AC33_START3[27]
#define BN0_WF_ARB_TOP_TQSW3_AC33_START3_SHFT                  27
#define BN0_WF_ARB_TOP_TQSW3_AC33_START2_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC33_START2_MASK                  0x04000000                // AC33_START2[26]
#define BN0_WF_ARB_TOP_TQSW3_AC33_START2_SHFT                  26
#define BN0_WF_ARB_TOP_TQSW3_AC33_START1_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC33_START1_MASK                  0x02000000                // AC33_START1[25]
#define BN0_WF_ARB_TOP_TQSW3_AC33_START1_SHFT                  25
#define BN0_WF_ARB_TOP_TQSW3_AC33_START0_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC33_START0_MASK                  0x01000000                // AC33_START0[24]
#define BN0_WF_ARB_TOP_TQSW3_AC33_START0_SHFT                  24
#define BN0_WF_ARB_TOP_TQSW3_AC32_START4_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC32_START4_MASK                  0x00100000                // AC32_START4[20]
#define BN0_WF_ARB_TOP_TQSW3_AC32_START4_SHFT                  20
#define BN0_WF_ARB_TOP_TQSW3_AC32_START3_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC32_START3_MASK                  0x00080000                // AC32_START3[19]
#define BN0_WF_ARB_TOP_TQSW3_AC32_START3_SHFT                  19
#define BN0_WF_ARB_TOP_TQSW3_AC32_START2_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC32_START2_MASK                  0x00040000                // AC32_START2[18]
#define BN0_WF_ARB_TOP_TQSW3_AC32_START2_SHFT                  18
#define BN0_WF_ARB_TOP_TQSW3_AC32_START1_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC32_START1_MASK                  0x00020000                // AC32_START1[17]
#define BN0_WF_ARB_TOP_TQSW3_AC32_START1_SHFT                  17
#define BN0_WF_ARB_TOP_TQSW3_AC32_START0_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC32_START0_MASK                  0x00010000                // AC32_START0[16]
#define BN0_WF_ARB_TOP_TQSW3_AC32_START0_SHFT                  16
#define BN0_WF_ARB_TOP_TQSW3_AC31_START4_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC31_START4_MASK                  0x00001000                // AC31_START4[12]
#define BN0_WF_ARB_TOP_TQSW3_AC31_START4_SHFT                  12
#define BN0_WF_ARB_TOP_TQSW3_AC31_START3_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC31_START3_MASK                  0x00000800                // AC31_START3[11]
#define BN0_WF_ARB_TOP_TQSW3_AC31_START3_SHFT                  11
#define BN0_WF_ARB_TOP_TQSW3_AC31_START2_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC31_START2_MASK                  0x00000400                // AC31_START2[10]
#define BN0_WF_ARB_TOP_TQSW3_AC31_START2_SHFT                  10
#define BN0_WF_ARB_TOP_TQSW3_AC31_START1_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC31_START1_MASK                  0x00000200                // AC31_START1[9]
#define BN0_WF_ARB_TOP_TQSW3_AC31_START1_SHFT                  9
#define BN0_WF_ARB_TOP_TQSW3_AC31_START0_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC31_START0_MASK                  0x00000100                // AC31_START0[8]
#define BN0_WF_ARB_TOP_TQSW3_AC31_START0_SHFT                  8
#define BN0_WF_ARB_TOP_TQSW3_AC30_START4_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC30_START4_MASK                  0x00000010                // AC30_START4[4]
#define BN0_WF_ARB_TOP_TQSW3_AC30_START4_SHFT                  4
#define BN0_WF_ARB_TOP_TQSW3_AC30_START3_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC30_START3_MASK                  0x00000008                // AC30_START3[3]
#define BN0_WF_ARB_TOP_TQSW3_AC30_START3_SHFT                  3
#define BN0_WF_ARB_TOP_TQSW3_AC30_START2_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC30_START2_MASK                  0x00000004                // AC30_START2[2]
#define BN0_WF_ARB_TOP_TQSW3_AC30_START2_SHFT                  2
#define BN0_WF_ARB_TOP_TQSW3_AC30_START1_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC30_START1_MASK                  0x00000002                // AC30_START1[1]
#define BN0_WF_ARB_TOP_TQSW3_AC30_START1_SHFT                  1
#define BN0_WF_ARB_TOP_TQSW3_AC30_START0_ADDR                  BN0_WF_ARB_TOP_TQSW3_ADDR
#define BN0_WF_ARB_TOP_TQSW3_AC30_START0_MASK                  0x00000001                // AC30_START0[0]
#define BN0_WF_ARB_TOP_TQSW3_AC30_START0_SHFT                  0

/* =====================================================================================

  ---TQSM0 (0x820E3000 + 0x110)---

    ALTX0_START0[0]              - (W1S) Same as AC00_START0~4
    ALTX0_START1[1]              - (W1S) Same as AC00_START0~4
    ALTX0_START2[2]              - (W1S) Same as AC00_START0~4
    ALTX0_START3[3]              - (W1S) Same as AC00_START0~4
    ALTX0_START4[4]              - (W1S) Same as AC00_START0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    BMC0_START0[8]               - (W1S) Same as AC00_START0~4
    BMC0_START1[9]               - (W1S) Same as AC00_START0~4
    BMC0_START2[10]              - (W1S) Same as AC00_START0~4
    BMC0_START3[11]              - (W1S) Same as AC00_START0~4
    RESERVED12[15..12]           - (RO) Reserved bits
    BCN0_START0[16]              - (W1S) Same as AC00_START0~4
    BCN0_START1[17]              - (W1S) Same as AC00_START0~4
    BCN0_START2[18]              - (W1S) Same as AC00_START0~4
    BCN0_START3[19]              - (W1S) Same as AC00_START0~4
    RESERVED20[23..20]           - (RO) Reserved bits
    PSMP0_START0[24]             - (W1S) Same as AC00_START0~4
    PSMP0_START1[25]             - (W1S) Same as AC00_START0~4
    PSMP0_START2[26]             - (W1S) Same as AC00_START0~4
    PSMP0_START3[27]             - (W1S) Same as AC00_START0~4
    PSMP0_START4[28]             - (W1S) Same as AC00_START0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START4_ADDR                 BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START4_MASK                 0x10000000                // PSMP0_START4[28]
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START4_SHFT                 28
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START3_ADDR                 BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START3_MASK                 0x08000000                // PSMP0_START3[27]
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START3_SHFT                 27
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START2_ADDR                 BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START2_MASK                 0x04000000                // PSMP0_START2[26]
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START2_SHFT                 26
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START1_ADDR                 BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START1_MASK                 0x02000000                // PSMP0_START1[25]
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START1_SHFT                 25
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START0_ADDR                 BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START0_MASK                 0x01000000                // PSMP0_START0[24]
#define BN0_WF_ARB_TOP_TQSM0_PSMP0_START0_SHFT                 24
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START3_ADDR                  BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START3_MASK                  0x00080000                // BCN0_START3[19]
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START3_SHFT                  19
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START2_ADDR                  BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START2_MASK                  0x00040000                // BCN0_START2[18]
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START2_SHFT                  18
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START1_ADDR                  BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START1_MASK                  0x00020000                // BCN0_START1[17]
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START1_SHFT                  17
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START0_ADDR                  BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START0_MASK                  0x00010000                // BCN0_START0[16]
#define BN0_WF_ARB_TOP_TQSM0_BCN0_START0_SHFT                  16
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START3_ADDR                  BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START3_MASK                  0x00000800                // BMC0_START3[11]
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START3_SHFT                  11
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START2_ADDR                  BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START2_MASK                  0x00000400                // BMC0_START2[10]
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START2_SHFT                  10
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START1_ADDR                  BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START1_MASK                  0x00000200                // BMC0_START1[9]
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START1_SHFT                  9
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START0_ADDR                  BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START0_MASK                  0x00000100                // BMC0_START0[8]
#define BN0_WF_ARB_TOP_TQSM0_BMC0_START0_SHFT                  8
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START4_ADDR                 BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START4_MASK                 0x00000010                // ALTX0_START4[4]
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START4_SHFT                 4
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START3_ADDR                 BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START3_MASK                 0x00000008                // ALTX0_START3[3]
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START3_SHFT                 3
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START2_ADDR                 BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START2_MASK                 0x00000004                // ALTX0_START2[2]
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START2_SHFT                 2
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START1_ADDR                 BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START1_MASK                 0x00000002                // ALTX0_START1[1]
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START1_SHFT                 1
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START0_ADDR                 BN0_WF_ARB_TOP_TQSM0_ADDR
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START0_MASK                 0x00000001                // ALTX0_START0[0]
#define BN0_WF_ARB_TOP_TQSM0_ALTX0_START0_SHFT                 0

/* =====================================================================================

  ---TQSE0 (0x820E3000 + 0x118)---

    RESERVED0[0]                 - (RO) Reserved bits
    BMC0_START0_1[1]             - (W1S) Same as AC00_START0~4
    BMC0_START0_2[2]             - (W1S) Same as AC00_START0~4
    BMC0_START0_3[3]             - (W1S) Same as AC00_START0~4
    BMC0_START0_4[4]             - (W1S) Same as AC00_START0~4
    BMC0_START0_5[5]             - (W1S) Same as AC00_START0~4
    BMC0_START0_6[6]             - (W1S) Same as AC00_START0~4
    BMC0_START0_7[7]             - (W1S) Same as AC00_START0~4
    BMC0_START0_8[8]             - (W1S) Same as AC00_START0~4
    BMC0_START0_9[9]             - (W1S) Same as AC00_START0~4
    BMC0_START0_10[10]           - (W1S) Same as AC00_START0~4
    BMC0_START0_11[11]           - (W1S) Same as AC00_START0~4
    BMC0_START0_12[12]           - (W1S) Same as AC00_START0~4
    BMC0_START0_13[13]           - (W1S) Same as AC00_START0~4
    BMC0_START0_14[14]           - (W1S) Same as AC00_START0~4
    BMC0_START0_15[15]           - (W1S) Same as AC00_START0~4
    RESERVED16[16]               - (RO) Reserved bits
    BCN0_START0_1[17]            - (W1S) Same as AC00_START0~4
    BCN0_START0_2[18]            - (W1S) Same as AC00_START0~4
    BCN0_START0_3[19]            - (W1S) Same as AC00_START0~4
    BCN0_START0_4[20]            - (W1S) Same as AC00_START0~4
    BCN0_START0_5[21]            - (W1S) Same as AC00_START0~4
    BCN0_START0_6[22]            - (W1S) Same as AC00_START0~4
    BCN0_START0_7[23]            - (W1S) Same as AC00_START0~4
    BCN0_START0_8[24]            - (W1S) Same as AC00_START0~4
    BCN0_START0_9[25]            - (W1S) Same as AC00_START0~4
    BCN0_START0_10[26]           - (W1S) Same as AC00_START0~4
    BCN0_START0_11[27]           - (W1S) Same as AC00_START0~4
    BCN0_START0_12[28]           - (W1S) Same as AC00_START0~4
    BCN0_START0_13[29]           - (W1S) Same as AC00_START0~4
    BCN0_START0_14[30]           - (W1S) Same as AC00_START0~4
    BCN0_START0_15[31]           - (W1S) Same as AC00_START0~4

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_15_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_15_MASK               0x80000000                // BCN0_START0_15[31]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_15_SHFT               31
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_14_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_14_MASK               0x40000000                // BCN0_START0_14[30]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_14_SHFT               30
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_13_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_13_MASK               0x20000000                // BCN0_START0_13[29]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_13_SHFT               29
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_12_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_12_MASK               0x10000000                // BCN0_START0_12[28]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_12_SHFT               28
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_11_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_11_MASK               0x08000000                // BCN0_START0_11[27]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_11_SHFT               27
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_10_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_10_MASK               0x04000000                // BCN0_START0_10[26]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_10_SHFT               26
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_9_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_9_MASK                0x02000000                // BCN0_START0_9[25]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_9_SHFT                25
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_8_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_8_MASK                0x01000000                // BCN0_START0_8[24]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_8_SHFT                24
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_7_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_7_MASK                0x00800000                // BCN0_START0_7[23]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_7_SHFT                23
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_6_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_6_MASK                0x00400000                // BCN0_START0_6[22]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_6_SHFT                22
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_5_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_5_MASK                0x00200000                // BCN0_START0_5[21]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_5_SHFT                21
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_4_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_4_MASK                0x00100000                // BCN0_START0_4[20]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_4_SHFT                20
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_3_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_3_MASK                0x00080000                // BCN0_START0_3[19]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_3_SHFT                19
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_2_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_2_MASK                0x00040000                // BCN0_START0_2[18]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_2_SHFT                18
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_1_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_1_MASK                0x00020000                // BCN0_START0_1[17]
#define BN0_WF_ARB_TOP_TQSE0_BCN0_START0_1_SHFT                17
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_15_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_15_MASK               0x00008000                // BMC0_START0_15[15]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_15_SHFT               15
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_14_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_14_MASK               0x00004000                // BMC0_START0_14[14]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_14_SHFT               14
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_13_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_13_MASK               0x00002000                // BMC0_START0_13[13]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_13_SHFT               13
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_12_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_12_MASK               0x00001000                // BMC0_START0_12[12]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_12_SHFT               12
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_11_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_11_MASK               0x00000800                // BMC0_START0_11[11]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_11_SHFT               11
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_10_ADDR               BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_10_MASK               0x00000400                // BMC0_START0_10[10]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_10_SHFT               10
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_9_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_9_MASK                0x00000200                // BMC0_START0_9[9]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_9_SHFT                9
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_8_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_8_MASK                0x00000100                // BMC0_START0_8[8]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_8_SHFT                8
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_7_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_7_MASK                0x00000080                // BMC0_START0_7[7]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_7_SHFT                7
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_6_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_6_MASK                0x00000040                // BMC0_START0_6[6]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_6_SHFT                6
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_5_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_5_MASK                0x00000020                // BMC0_START0_5[5]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_5_SHFT                5
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_4_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_4_MASK                0x00000010                // BMC0_START0_4[4]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_4_SHFT                4
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_3_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_3_MASK                0x00000008                // BMC0_START0_3[3]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_3_SHFT                3
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_2_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_2_MASK                0x00000004                // BMC0_START0_2[2]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_2_SHFT                2
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_1_ADDR                BN0_WF_ARB_TOP_TQSE0_ADDR
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_1_MASK                0x00000002                // BMC0_START0_1[1]
#define BN0_WF_ARB_TOP_TQSE0_BMC0_START0_1_SHFT                1

/* =====================================================================================

  ---TQFW0 (0x820E3000 + 0x120)---

    AC00_FLUSH0[0]               - (W1S) Stop the AC00 BSSID0 queue operation, and once one of the AC00_FLUSH0~4 is enabled, AC00 queue will be flushed.
                                     The current transmitting packet will be aborted and will not retry to send this packet anymore.
                                     Write 0 is meaningless. Read will indicate the FIFO flush status of this queue.
                                     0: not under flush or flush completed (cleared by HW)
                                     1: under flush (set by FW)
    AC00_FLUSH1[1]               - (W1S) Stop the AC00 BSSID1 queue operate and flush AC00
                                     Same as AC00_FLUSH0
    AC00_FLUSH2[2]               - (W1S) Stop the AC00 BSSID2 queue operate and flush AC00
                                     Same as AC00_FLUSH0
    AC00_FLUSH3[3]               - (W1S) Stop the AC00 BSSID3 queue operate and flush AC00
                                     Same as AC00_FLUSH0
    AC00_FLUSH4[4]               - (W1S) Stop the AC00 BSSID4 queue operate and flush AC00
                                     Same as AC00_FLUSH0
    RESERVED5[7..5]              - (RO) Reserved bits
    AC01_FLUSH0[8]               - (W1S) Same as AC00_FLUSH0~4
    AC01_FLUSH1[9]               - (W1S) Same as AC00_FLUSH0~4
    AC01_FLUSH2[10]              - (W1S) Same as AC00_FLUSH0~4
    AC01_FLUSH3[11]              - (W1S) Same as AC00_FLUSH0~4
    AC01_FLUSH4[12]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC02_FLUSH0[16]              - (W1S) Same as AC00_FLUSH0~4
    AC02_FLUSH1[17]              - (W1S) Same as AC00_FLUSH0~4
    AC02_FLUSH2[18]              - (W1S) Same as AC00_FLUSH0~4
    AC02_FLUSH3[19]              - (W1S) Same as AC00_FLUSH0~4
    AC02_FLUSH4[20]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC03_FLUSH0[24]              - (W1S) Same as AC00_FLUSH0~4
    AC03_FLUSH1[25]              - (W1S) Same as AC00_FLUSH0~4
    AC03_FLUSH2[26]              - (W1S) Same as AC00_FLUSH0~4
    AC03_FLUSH3[27]              - (W1S) Same as AC00_FLUSH0~4
    AC03_FLUSH4[28]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH4_MASK                  0x10000000                // AC03_FLUSH4[28]
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH4_SHFT                  28
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH3_MASK                  0x08000000                // AC03_FLUSH3[27]
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH3_SHFT                  27
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH2_MASK                  0x04000000                // AC03_FLUSH2[26]
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH2_SHFT                  26
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH1_MASK                  0x02000000                // AC03_FLUSH1[25]
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH1_SHFT                  25
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH0_MASK                  0x01000000                // AC03_FLUSH0[24]
#define BN0_WF_ARB_TOP_TQFW0_AC03_FLUSH0_SHFT                  24
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH4_MASK                  0x00100000                // AC02_FLUSH4[20]
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH4_SHFT                  20
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH3_MASK                  0x00080000                // AC02_FLUSH3[19]
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH3_SHFT                  19
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH2_MASK                  0x00040000                // AC02_FLUSH2[18]
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH2_SHFT                  18
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH1_MASK                  0x00020000                // AC02_FLUSH1[17]
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH1_SHFT                  17
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH0_MASK                  0x00010000                // AC02_FLUSH0[16]
#define BN0_WF_ARB_TOP_TQFW0_AC02_FLUSH0_SHFT                  16
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH4_MASK                  0x00001000                // AC01_FLUSH4[12]
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH4_SHFT                  12
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH3_MASK                  0x00000800                // AC01_FLUSH3[11]
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH3_SHFT                  11
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH2_MASK                  0x00000400                // AC01_FLUSH2[10]
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH2_SHFT                  10
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH1_MASK                  0x00000200                // AC01_FLUSH1[9]
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH1_SHFT                  9
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH0_MASK                  0x00000100                // AC01_FLUSH0[8]
#define BN0_WF_ARB_TOP_TQFW0_AC01_FLUSH0_SHFT                  8
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH4_MASK                  0x00000010                // AC00_FLUSH4[4]
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH4_SHFT                  4
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH3_MASK                  0x00000008                // AC00_FLUSH3[3]
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH3_SHFT                  3
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH2_MASK                  0x00000004                // AC00_FLUSH2[2]
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH2_SHFT                  2
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH1_MASK                  0x00000002                // AC00_FLUSH1[1]
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH1_SHFT                  1
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW0_ADDR
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH0_MASK                  0x00000001                // AC00_FLUSH0[0]
#define BN0_WF_ARB_TOP_TQFW0_AC00_FLUSH0_SHFT                  0

/* =====================================================================================

  ---TQFW1 (0x820E3000 + 0x124)---

    AC10_FLUSH0[0]               - (W1S) Same as AC00_FLUSH0~4
    AC10_FLUSH1[1]               - (W1S) Same as AC00_FLUSH0~4
    AC10_FLUSH2[2]               - (W1S) Same as AC00_FLUSH0~4
    AC10_FLUSH3[3]               - (W1S) Same as AC00_FLUSH0~4
    AC10_FLUSH4[4]               - (W1S) Same as AC00_FLUSH0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    AC11_FLUSH0[8]               - (W1S) Same as AC00_FLUSH0~4
    AC11_FLUSH1[9]               - (W1S) Same as AC00_FLUSH0~4
    AC11_FLUSH2[10]              - (W1S) Same as AC00_FLUSH0~4
    AC11_FLUSH3[11]              - (W1S) Same as AC00_FLUSH0~4
    AC11_FLUSH4[12]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC12_FLUSH0[16]              - (W1S) Same as AC00_FLUSH0~4
    AC12_FLUSH1[17]              - (W1S) Same as AC00_FLUSH0~4
    AC12_FLUSH2[18]              - (W1S) Same as AC00_FLUSH0~4
    AC12_FLUSH3[19]              - (W1S) Same as AC00_FLUSH0~4
    AC12_FLUSH4[20]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC13_FLUSH0[24]              - (W1S) Same as AC00_FLUSH0~4
    AC13_FLUSH1[25]              - (W1S) Same as AC00_FLUSH0~4
    AC13_FLUSH2[26]              - (W1S) Same as AC00_FLUSH0~4
    AC13_FLUSH3[27]              - (W1S) Same as AC00_FLUSH0~4
    AC13_FLUSH4[28]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH4_MASK                  0x10000000                // AC13_FLUSH4[28]
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH4_SHFT                  28
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH3_MASK                  0x08000000                // AC13_FLUSH3[27]
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH3_SHFT                  27
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH2_MASK                  0x04000000                // AC13_FLUSH2[26]
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH2_SHFT                  26
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH1_MASK                  0x02000000                // AC13_FLUSH1[25]
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH1_SHFT                  25
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH0_MASK                  0x01000000                // AC13_FLUSH0[24]
#define BN0_WF_ARB_TOP_TQFW1_AC13_FLUSH0_SHFT                  24
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH4_MASK                  0x00100000                // AC12_FLUSH4[20]
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH4_SHFT                  20
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH3_MASK                  0x00080000                // AC12_FLUSH3[19]
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH3_SHFT                  19
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH2_MASK                  0x00040000                // AC12_FLUSH2[18]
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH2_SHFT                  18
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH1_MASK                  0x00020000                // AC12_FLUSH1[17]
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH1_SHFT                  17
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH0_MASK                  0x00010000                // AC12_FLUSH0[16]
#define BN0_WF_ARB_TOP_TQFW1_AC12_FLUSH0_SHFT                  16
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH4_MASK                  0x00001000                // AC11_FLUSH4[12]
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH4_SHFT                  12
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH3_MASK                  0x00000800                // AC11_FLUSH3[11]
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH3_SHFT                  11
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH2_MASK                  0x00000400                // AC11_FLUSH2[10]
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH2_SHFT                  10
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH1_MASK                  0x00000200                // AC11_FLUSH1[9]
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH1_SHFT                  9
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH0_MASK                  0x00000100                // AC11_FLUSH0[8]
#define BN0_WF_ARB_TOP_TQFW1_AC11_FLUSH0_SHFT                  8
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH4_MASK                  0x00000010                // AC10_FLUSH4[4]
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH4_SHFT                  4
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH3_MASK                  0x00000008                // AC10_FLUSH3[3]
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH3_SHFT                  3
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH2_MASK                  0x00000004                // AC10_FLUSH2[2]
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH2_SHFT                  2
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH1_MASK                  0x00000002                // AC10_FLUSH1[1]
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH1_SHFT                  1
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW1_ADDR
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH0_MASK                  0x00000001                // AC10_FLUSH0[0]
#define BN0_WF_ARB_TOP_TQFW1_AC10_FLUSH0_SHFT                  0

/* =====================================================================================

  ---TQFW2 (0x820E3000 + 0x128)---

    AC20_FLUSH0[0]               - (W1S) Same as AC00_FLUSH0~4
    AC20_FLUSH1[1]               - (W1S) Same as AC00_FLUSH0~4
    AC20_FLUSH2[2]               - (W1S) Same as AC00_FLUSH0~4
    AC20_FLUSH3[3]               - (W1S) Same as AC00_FLUSH0~4
    AC20_FLUSH4[4]               - (W1S) Same as AC00_FLUSH0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    AC21_FLUSH0[8]               - (W1S) Same as AC00_FLUSH0~4
    AC21_FLUSH1[9]               - (W1S) Same as AC00_FLUSH0~4
    AC21_FLUSH2[10]              - (W1S) Same as AC00_FLUSH0~4
    AC21_FLUSH3[11]              - (W1S) Same as AC00_FLUSH0~4
    AC21_FLUSH4[12]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC22_FLUSH0[16]              - (W1S) Same as AC00_FLUSH0~4
    AC22_FLUSH1[17]              - (W1S) Same as AC00_FLUSH0~4
    AC22_FLUSH2[18]              - (W1S) Same as AC00_FLUSH0~4
    AC22_FLUSH3[19]              - (W1S) Same as AC00_FLUSH0~4
    AC22_FLUSH4[20]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC23_FLUSH0[24]              - (W1S) Same as AC00_FLUSH0~4
    AC23_FLUSH1[25]              - (W1S) Same as AC00_FLUSH0~4
    AC23_FLUSH2[26]              - (W1S) Same as AC00_FLUSH0~4
    AC23_FLUSH3[27]              - (W1S) Same as AC00_FLUSH0~4
    AC23_FLUSH4[28]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH4_MASK                  0x10000000                // AC23_FLUSH4[28]
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH4_SHFT                  28
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH3_MASK                  0x08000000                // AC23_FLUSH3[27]
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH3_SHFT                  27
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH2_MASK                  0x04000000                // AC23_FLUSH2[26]
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH2_SHFT                  26
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH1_MASK                  0x02000000                // AC23_FLUSH1[25]
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH1_SHFT                  25
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH0_MASK                  0x01000000                // AC23_FLUSH0[24]
#define BN0_WF_ARB_TOP_TQFW2_AC23_FLUSH0_SHFT                  24
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH4_MASK                  0x00100000                // AC22_FLUSH4[20]
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH4_SHFT                  20
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH3_MASK                  0x00080000                // AC22_FLUSH3[19]
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH3_SHFT                  19
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH2_MASK                  0x00040000                // AC22_FLUSH2[18]
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH2_SHFT                  18
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH1_MASK                  0x00020000                // AC22_FLUSH1[17]
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH1_SHFT                  17
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH0_MASK                  0x00010000                // AC22_FLUSH0[16]
#define BN0_WF_ARB_TOP_TQFW2_AC22_FLUSH0_SHFT                  16
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH4_MASK                  0x00001000                // AC21_FLUSH4[12]
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH4_SHFT                  12
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH3_MASK                  0x00000800                // AC21_FLUSH3[11]
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH3_SHFT                  11
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH2_MASK                  0x00000400                // AC21_FLUSH2[10]
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH2_SHFT                  10
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH1_MASK                  0x00000200                // AC21_FLUSH1[9]
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH1_SHFT                  9
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH0_MASK                  0x00000100                // AC21_FLUSH0[8]
#define BN0_WF_ARB_TOP_TQFW2_AC21_FLUSH0_SHFT                  8
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH4_MASK                  0x00000010                // AC20_FLUSH4[4]
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH4_SHFT                  4
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH3_MASK                  0x00000008                // AC20_FLUSH3[3]
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH3_SHFT                  3
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH2_MASK                  0x00000004                // AC20_FLUSH2[2]
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH2_SHFT                  2
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH1_MASK                  0x00000002                // AC20_FLUSH1[1]
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH1_SHFT                  1
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW2_ADDR
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH0_MASK                  0x00000001                // AC20_FLUSH0[0]
#define BN0_WF_ARB_TOP_TQFW2_AC20_FLUSH0_SHFT                  0

/* =====================================================================================

  ---TQFW3 (0x820E3000 + 0x12C)---

    AC30_FLUSH0[0]               - (W1S) Same as AC00_FLUSH0~4
    AC30_FLUSH1[1]               - (W1S) Same as AC00_FLUSH0~4
    AC30_FLUSH2[2]               - (W1S) Same as AC00_FLUSH0~4
    AC30_FLUSH3[3]               - (W1S) Same as AC00_FLUSH0~4
    AC30_FLUSH4[4]               - (W1S) Same as AC00_FLUSH0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    AC31_FLUSH0[8]               - (W1S) Same as AC00_FLUSH0~4
    AC31_FLUSH1[9]               - (W1S) Same as AC00_FLUSH0~4
    AC31_FLUSH2[10]              - (W1S) Same as AC00_FLUSH0~4
    AC31_FLUSH3[11]              - (W1S) Same as AC00_FLUSH0~4
    AC31_FLUSH4[12]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC32_FLUSH0[16]              - (W1S) Same as AC00_FLUSH0~4
    AC32_FLUSH1[17]              - (W1S) Same as AC00_FLUSH0~4
    AC32_FLUSH2[18]              - (W1S) Same as AC00_FLUSH0~4
    AC32_FLUSH3[19]              - (W1S) Same as AC00_FLUSH0~4
    AC32_FLUSH4[20]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC33_FLUSH0[24]              - (W1S) Same as AC00_FLUSH0~4
    AC33_FLUSH1[25]              - (W1S) Same as AC00_FLUSH0~4
    AC33_FLUSH2[26]              - (W1S) Same as AC00_FLUSH0~4
    AC33_FLUSH3[27]              - (W1S) Same as AC00_FLUSH0~4
    AC33_FLUSH4[28]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH4_MASK                  0x10000000                // AC33_FLUSH4[28]
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH4_SHFT                  28
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH3_MASK                  0x08000000                // AC33_FLUSH3[27]
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH3_SHFT                  27
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH2_MASK                  0x04000000                // AC33_FLUSH2[26]
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH2_SHFT                  26
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH1_MASK                  0x02000000                // AC33_FLUSH1[25]
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH1_SHFT                  25
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH0_MASK                  0x01000000                // AC33_FLUSH0[24]
#define BN0_WF_ARB_TOP_TQFW3_AC33_FLUSH0_SHFT                  24
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH4_MASK                  0x00100000                // AC32_FLUSH4[20]
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH4_SHFT                  20
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH3_MASK                  0x00080000                // AC32_FLUSH3[19]
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH3_SHFT                  19
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH2_MASK                  0x00040000                // AC32_FLUSH2[18]
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH2_SHFT                  18
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH1_MASK                  0x00020000                // AC32_FLUSH1[17]
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH1_SHFT                  17
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH0_MASK                  0x00010000                // AC32_FLUSH0[16]
#define BN0_WF_ARB_TOP_TQFW3_AC32_FLUSH0_SHFT                  16
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH4_MASK                  0x00001000                // AC31_FLUSH4[12]
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH4_SHFT                  12
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH3_MASK                  0x00000800                // AC31_FLUSH3[11]
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH3_SHFT                  11
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH2_MASK                  0x00000400                // AC31_FLUSH2[10]
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH2_SHFT                  10
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH1_MASK                  0x00000200                // AC31_FLUSH1[9]
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH1_SHFT                  9
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH0_MASK                  0x00000100                // AC31_FLUSH0[8]
#define BN0_WF_ARB_TOP_TQFW3_AC31_FLUSH0_SHFT                  8
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH4_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH4_MASK                  0x00000010                // AC30_FLUSH4[4]
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH4_SHFT                  4
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH3_MASK                  0x00000008                // AC30_FLUSH3[3]
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH3_SHFT                  3
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH2_MASK                  0x00000004                // AC30_FLUSH2[2]
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH2_SHFT                  2
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH1_MASK                  0x00000002                // AC30_FLUSH1[1]
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH1_SHFT                  1
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFW3_ADDR
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH0_MASK                  0x00000001                // AC30_FLUSH0[0]
#define BN0_WF_ARB_TOP_TQFW3_AC30_FLUSH0_SHFT                  0

/* =====================================================================================

  ---TQFM0 (0x820E3000 + 0x130)---

    ALTX0_FLUSH0[0]              - (W1S) Same as AC00_FLUSH0~4
    ALTX0_FLUSH1[1]              - (W1S) Same as AC00_FLUSH0~4
    ALTX0_FLUSH2[2]              - (W1S) Same as AC00_FLUSH0~4
    ALTX0_FLUSH3[3]              - (W1S) Same as AC00_FLUSH0~4
    ALTX0_FLUSH4[4]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    BMC0_FLUSH0[8]               - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH1[9]               - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH2[10]              - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH3[11]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED12[15..12]           - (RO) Reserved bits
    BCN0_FLUSH0[16]              - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH1[17]              - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH2[18]              - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH3[19]              - (W1S) Same as AC00_FLUSH0~4
    RESERVED20[23..20]           - (RO) Reserved bits
    PSMP0_FLUSH0[24]             - (W1S) Same as AC00_FLUSH0~4
    PSMP0_FLUSH1[25]             - (W1S) Same as AC00_FLUSH0~4
    PSMP0_FLUSH2[26]             - (W1S) Same as AC00_FLUSH0~4
    PSMP0_FLUSH3[27]             - (W1S) Same as AC00_FLUSH0~4
    PSMP0_FLUSH4[28]             - (W1S) Same as AC00_FLUSH0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH4_ADDR                 BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH4_MASK                 0x10000000                // PSMP0_FLUSH4[28]
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH4_SHFT                 28
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH3_ADDR                 BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH3_MASK                 0x08000000                // PSMP0_FLUSH3[27]
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH3_SHFT                 27
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH2_ADDR                 BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH2_MASK                 0x04000000                // PSMP0_FLUSH2[26]
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH2_SHFT                 26
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH1_ADDR                 BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH1_MASK                 0x02000000                // PSMP0_FLUSH1[25]
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH1_SHFT                 25
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH0_ADDR                 BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH0_MASK                 0x01000000                // PSMP0_FLUSH0[24]
#define BN0_WF_ARB_TOP_TQFM0_PSMP0_FLUSH0_SHFT                 24
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH3_MASK                  0x00080000                // BCN0_FLUSH3[19]
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH3_SHFT                  19
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH2_MASK                  0x00040000                // BCN0_FLUSH2[18]
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH2_SHFT                  18
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH1_MASK                  0x00020000                // BCN0_FLUSH1[17]
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH1_SHFT                  17
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH0_MASK                  0x00010000                // BCN0_FLUSH0[16]
#define BN0_WF_ARB_TOP_TQFM0_BCN0_FLUSH0_SHFT                  16
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH3_ADDR                  BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH3_MASK                  0x00000800                // BMC0_FLUSH3[11]
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH3_SHFT                  11
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH2_ADDR                  BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH2_MASK                  0x00000400                // BMC0_FLUSH2[10]
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH2_SHFT                  10
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH1_ADDR                  BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH1_MASK                  0x00000200                // BMC0_FLUSH1[9]
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH1_SHFT                  9
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH0_ADDR                  BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH0_MASK                  0x00000100                // BMC0_FLUSH0[8]
#define BN0_WF_ARB_TOP_TQFM0_BMC0_FLUSH0_SHFT                  8
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH4_ADDR                 BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH4_MASK                 0x00000010                // ALTX0_FLUSH4[4]
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH4_SHFT                 4
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH3_ADDR                 BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH3_MASK                 0x00000008                // ALTX0_FLUSH3[3]
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH3_SHFT                 3
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH2_ADDR                 BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH2_MASK                 0x00000004                // ALTX0_FLUSH2[2]
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH2_SHFT                 2
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH1_ADDR                 BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH1_MASK                 0x00000002                // ALTX0_FLUSH1[1]
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH1_SHFT                 1
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH0_ADDR                 BN0_WF_ARB_TOP_TQFM0_ADDR
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH0_MASK                 0x00000001                // ALTX0_FLUSH0[0]
#define BN0_WF_ARB_TOP_TQFM0_ALTX0_FLUSH0_SHFT                 0

/* =====================================================================================

  ---TQFE0 (0x820E3000 + 0x138)---

    RESERVED0[0]                 - (RO) Reserved bits
    BMC0_FLUSH0_1[1]             - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_2[2]             - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_3[3]             - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_4[4]             - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_5[5]             - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_6[6]             - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_7[7]             - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_8[8]             - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_9[9]             - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_10[10]           - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_11[11]           - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_12[12]           - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_13[13]           - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_14[14]           - (W1S) Same as AC00_FLUSH0~4
    BMC0_FLUSH0_15[15]           - (W1S) Same as AC00_FLUSH0~4
    RESERVED16[16]               - (RO) Reserved bits
    BCN0_FLUSH0_1[17]            - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_2[18]            - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_3[19]            - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_4[20]            - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_5[21]            - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_6[22]            - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_7[23]            - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_8[24]            - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_9[25]            - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_10[26]           - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_11[27]           - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_12[28]           - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_13[29]           - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_14[30]           - (W1S) Same as AC00_FLUSH0~4
    BCN0_FLUSH0_15[31]           - (W1S) Same as AC00_FLUSH0~4

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_15_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_15_MASK               0x80000000                // BCN0_FLUSH0_15[31]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_15_SHFT               31
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_14_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_14_MASK               0x40000000                // BCN0_FLUSH0_14[30]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_14_SHFT               30
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_13_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_13_MASK               0x20000000                // BCN0_FLUSH0_13[29]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_13_SHFT               29
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_12_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_12_MASK               0x10000000                // BCN0_FLUSH0_12[28]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_12_SHFT               28
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_11_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_11_MASK               0x08000000                // BCN0_FLUSH0_11[27]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_11_SHFT               27
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_10_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_10_MASK               0x04000000                // BCN0_FLUSH0_10[26]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_10_SHFT               26
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_9_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_9_MASK                0x02000000                // BCN0_FLUSH0_9[25]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_9_SHFT                25
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_8_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_8_MASK                0x01000000                // BCN0_FLUSH0_8[24]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_8_SHFT                24
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_7_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_7_MASK                0x00800000                // BCN0_FLUSH0_7[23]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_7_SHFT                23
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_6_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_6_MASK                0x00400000                // BCN0_FLUSH0_6[22]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_6_SHFT                22
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_5_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_5_MASK                0x00200000                // BCN0_FLUSH0_5[21]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_5_SHFT                21
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_4_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_4_MASK                0x00100000                // BCN0_FLUSH0_4[20]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_4_SHFT                20
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_3_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_3_MASK                0x00080000                // BCN0_FLUSH0_3[19]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_3_SHFT                19
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_2_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_2_MASK                0x00040000                // BCN0_FLUSH0_2[18]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_2_SHFT                18
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_1_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_1_MASK                0x00020000                // BCN0_FLUSH0_1[17]
#define BN0_WF_ARB_TOP_TQFE0_BCN0_FLUSH0_1_SHFT                17
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_15_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_15_MASK               0x00008000                // BMC0_FLUSH0_15[15]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_15_SHFT               15
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_14_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_14_MASK               0x00004000                // BMC0_FLUSH0_14[14]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_14_SHFT               14
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_13_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_13_MASK               0x00002000                // BMC0_FLUSH0_13[13]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_13_SHFT               13
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_12_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_12_MASK               0x00001000                // BMC0_FLUSH0_12[12]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_12_SHFT               12
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_11_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_11_MASK               0x00000800                // BMC0_FLUSH0_11[11]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_11_SHFT               11
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_10_ADDR               BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_10_MASK               0x00000400                // BMC0_FLUSH0_10[10]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_10_SHFT               10
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_9_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_9_MASK                0x00000200                // BMC0_FLUSH0_9[9]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_9_SHFT                9
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_8_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_8_MASK                0x00000100                // BMC0_FLUSH0_8[8]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_8_SHFT                8
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_7_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_7_MASK                0x00000080                // BMC0_FLUSH0_7[7]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_7_SHFT                7
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_6_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_6_MASK                0x00000040                // BMC0_FLUSH0_6[6]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_6_SHFT                6
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_5_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_5_MASK                0x00000020                // BMC0_FLUSH0_5[5]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_5_SHFT                5
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_4_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_4_MASK                0x00000010                // BMC0_FLUSH0_4[4]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_4_SHFT                4
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_3_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_3_MASK                0x00000008                // BMC0_FLUSH0_3[3]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_3_SHFT                3
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_2_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_2_MASK                0x00000004                // BMC0_FLUSH0_2[2]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_2_SHFT                2
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_1_ADDR                BN0_WF_ARB_TOP_TQFE0_ADDR
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_1_MASK                0x00000002                // BMC0_FLUSH0_1[1]
#define BN0_WF_ARB_TOP_TQFE0_BMC0_FLUSH0_1_SHFT                1

/* =====================================================================================

  ---TQPW0 (0x820E3000 + 0x140)---

    AC00_STOP0[0]                - (W1S) Pause the AC0 BSSID0 queue operation.
                                     Write 1 to stop the queue. The current transmitting packet will be aborted and the remaining packets in this queue will not be transmitted. If TX status has been received before this queue been stopped (The packet has been transmitted or timeout) and not written to SYSRAM yet, the status will not be affected by AC00_STOP and will be moved to SYSRAM, and a TX done interrupt will still be issued later. 
                                     Write 0 is meaningless. Read will indicate the FIFO stop status of this queue.
                                     0: not under stop or queue stopped. (cleared by HW)
                                     1: under stop (set by FW)
    AC00_STOP1[1]                - (W1S) Pause the AC00 BSSID1 queue operate
                                     Same as AC00_STOP0
    AC00_STOP2[2]                - (W1S) Pause the AC00 BSSID2 queue operate
                                     Same as AC00_STOP0
    AC00_STOP3[3]                - (W1S) Pause the AC00 BSSID3 queue operate
                                     Same as AC00_STOP0
    AC00_STOP4[4]                - (W1S) Pause the AC00 BSSID4 queue operate
                                     Same as AC00_STOP0
    RESERVED5[7..5]              - (RO) Reserved bits
    AC01_STOP0[8]                - (W1S) Same as AC00_STOP0~4
    AC01_STOP1[9]                - (W1S) Same as AC00_STOP0~4
    AC01_STOP2[10]               - (W1S) Same as AC00_STOP0~4
    AC01_STOP3[11]               - (W1S) Same as AC00_STOP0~4
    AC01_STOP4[12]               - (W1S) Same as AC00_STOP0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC02_STOP0[16]               - (W1S) Same as AC00_STOP0~4
    AC02_STOP1[17]               - (W1S) Same as AC00_STOP0~4
    AC02_STOP2[18]               - (W1S) Same as AC00_STOP0~4
    AC02_STOP3[19]               - (W1S) Same as AC00_STOP0~4
    AC02_STOP4[20]               - (W1S) Same as AC00_STOP0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC03_STOP0[24]               - (W1S) Same as AC00_STOP0~4
    AC03_STOP1[25]               - (W1S) Same as AC00_STOP0~4
    AC03_STOP2[26]               - (W1S) Same as AC00_STOP0~4
    AC03_STOP3[27]               - (W1S) Same as AC00_STOP0~4
    AC03_STOP4[28]               - (W1S) Same as AC00_STOP0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP4_MASK                   0x10000000                // AC03_STOP4[28]
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP4_SHFT                   28
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP3_MASK                   0x08000000                // AC03_STOP3[27]
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP3_SHFT                   27
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP2_MASK                   0x04000000                // AC03_STOP2[26]
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP2_SHFT                   26
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP1_MASK                   0x02000000                // AC03_STOP1[25]
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP1_SHFT                   25
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP0_MASK                   0x01000000                // AC03_STOP0[24]
#define BN0_WF_ARB_TOP_TQPW0_AC03_STOP0_SHFT                   24
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP4_MASK                   0x00100000                // AC02_STOP4[20]
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP4_SHFT                   20
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP3_MASK                   0x00080000                // AC02_STOP3[19]
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP3_SHFT                   19
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP2_MASK                   0x00040000                // AC02_STOP2[18]
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP2_SHFT                   18
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP1_MASK                   0x00020000                // AC02_STOP1[17]
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP1_SHFT                   17
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP0_MASK                   0x00010000                // AC02_STOP0[16]
#define BN0_WF_ARB_TOP_TQPW0_AC02_STOP0_SHFT                   16
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP4_MASK                   0x00001000                // AC01_STOP4[12]
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP4_SHFT                   12
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP3_MASK                   0x00000800                // AC01_STOP3[11]
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP3_SHFT                   11
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP2_MASK                   0x00000400                // AC01_STOP2[10]
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP2_SHFT                   10
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP1_MASK                   0x00000200                // AC01_STOP1[9]
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP1_SHFT                   9
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP0_MASK                   0x00000100                // AC01_STOP0[8]
#define BN0_WF_ARB_TOP_TQPW0_AC01_STOP0_SHFT                   8
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP4_MASK                   0x00000010                // AC00_STOP4[4]
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP4_SHFT                   4
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP3_MASK                   0x00000008                // AC00_STOP3[3]
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP3_SHFT                   3
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP2_MASK                   0x00000004                // AC00_STOP2[2]
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP2_SHFT                   2
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP1_MASK                   0x00000002                // AC00_STOP1[1]
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP1_SHFT                   1
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW0_ADDR
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP0_MASK                   0x00000001                // AC00_STOP0[0]
#define BN0_WF_ARB_TOP_TQPW0_AC00_STOP0_SHFT                   0

/* =====================================================================================

  ---TQPW1 (0x820E3000 + 0x144)---

    AC10_STOP0[0]                - (W1S) Same as AC00_STOP0~4
    AC10_STOP1[1]                - (W1S) Same as AC00_STOP0~4
    AC10_STOP2[2]                - (W1S) Same as AC00_STOP0~4
    AC10_STOP3[3]                - (W1S) Same as AC00_STOP0~4
    AC10_STOP4[4]                - (W1S) Same as AC00_STOP0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    AC11_STOP0[8]                - (W1S) Same as AC00_STOP0~4
    AC11_STOP1[9]                - (W1S) Same as AC00_STOP0~4
    AC11_STOP2[10]               - (W1S) Same as AC00_STOP0~4
    AC11_STOP3[11]               - (W1S) Same as AC00_STOP0~4
    AC11_STOP4[12]               - (W1S) Same as AC00_STOP0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC12_STOP0[16]               - (W1S) Same as AC00_STOP0~4
    AC12_STOP1[17]               - (W1S) Same as AC00_STOP0~4
    AC12_STOP2[18]               - (W1S) Same as AC00_STOP0~4
    AC12_STOP3[19]               - (W1S) Same as AC00_STOP0~4
    AC12_STOP4[20]               - (W1S) Same as AC00_STOP0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC13_STOP0[24]               - (W1S) Same as AC00_STOP0~4
    AC13_STOP1[25]               - (W1S) Same as AC00_STOP0~4
    AC13_STOP2[26]               - (W1S) Same as AC00_STOP0~4
    AC13_STOP3[27]               - (W1S) Same as AC00_STOP0~4
    AC13_STOP4[28]               - (W1S) Same as AC00_STOP0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP4_MASK                   0x10000000                // AC13_STOP4[28]
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP4_SHFT                   28
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP3_MASK                   0x08000000                // AC13_STOP3[27]
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP3_SHFT                   27
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP2_MASK                   0x04000000                // AC13_STOP2[26]
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP2_SHFT                   26
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP1_MASK                   0x02000000                // AC13_STOP1[25]
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP1_SHFT                   25
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP0_MASK                   0x01000000                // AC13_STOP0[24]
#define BN0_WF_ARB_TOP_TQPW1_AC13_STOP0_SHFT                   24
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP4_MASK                   0x00100000                // AC12_STOP4[20]
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP4_SHFT                   20
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP3_MASK                   0x00080000                // AC12_STOP3[19]
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP3_SHFT                   19
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP2_MASK                   0x00040000                // AC12_STOP2[18]
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP2_SHFT                   18
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP1_MASK                   0x00020000                // AC12_STOP1[17]
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP1_SHFT                   17
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP0_MASK                   0x00010000                // AC12_STOP0[16]
#define BN0_WF_ARB_TOP_TQPW1_AC12_STOP0_SHFT                   16
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP4_MASK                   0x00001000                // AC11_STOP4[12]
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP4_SHFT                   12
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP3_MASK                   0x00000800                // AC11_STOP3[11]
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP3_SHFT                   11
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP2_MASK                   0x00000400                // AC11_STOP2[10]
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP2_SHFT                   10
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP1_MASK                   0x00000200                // AC11_STOP1[9]
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP1_SHFT                   9
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP0_MASK                   0x00000100                // AC11_STOP0[8]
#define BN0_WF_ARB_TOP_TQPW1_AC11_STOP0_SHFT                   8
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP4_MASK                   0x00000010                // AC10_STOP4[4]
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP4_SHFT                   4
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP3_MASK                   0x00000008                // AC10_STOP3[3]
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP3_SHFT                   3
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP2_MASK                   0x00000004                // AC10_STOP2[2]
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP2_SHFT                   2
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP1_MASK                   0x00000002                // AC10_STOP1[1]
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP1_SHFT                   1
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW1_ADDR
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP0_MASK                   0x00000001                // AC10_STOP0[0]
#define BN0_WF_ARB_TOP_TQPW1_AC10_STOP0_SHFT                   0

/* =====================================================================================

  ---TQPW2 (0x820E3000 + 0x148)---

    AC20_STOP0[0]                - (W1S) Same as AC00_STOP0~4
    AC20_STOP1[1]                - (W1S) Same as AC00_STOP0~4
    AC20_STOP2[2]                - (W1S) Same as AC00_STOP0~4
    AC20_STOP3[3]                - (W1S) Same as AC00_STOP0~4
    AC20_STOP4[4]                - (W1S) Same as AC00_STOP0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    AC21_STOP0[8]                - (W1S) Same as AC00_STOP0~4
    AC21_STOP1[9]                - (W1S) Same as AC00_STOP0~4
    AC21_STOP2[10]               - (W1S) Same as AC00_STOP0~4
    AC21_STOP3[11]               - (W1S) Same as AC00_STOP0~4
    AC21_STOP4[12]               - (W1S) Same as AC00_STOP0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC22_STOP0[16]               - (W1S) Same as AC00_STOP0~4
    AC22_STOP1[17]               - (W1S) Same as AC00_STOP0~4
    AC22_STOP2[18]               - (W1S) Same as AC00_STOP0~4
    AC22_STOP3[19]               - (W1S) Same as AC00_STOP0~4
    AC22_STOP4[20]               - (W1S) Same as AC00_STOP0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC23_STOP0[24]               - (W1S) Same as AC00_STOP0~4
    AC23_STOP1[25]               - (W1S) Same as AC00_STOP0~4
    AC23_STOP2[26]               - (W1S) Same as AC00_STOP0~4
    AC23_STOP3[27]               - (W1S) Same as AC00_STOP0~4
    AC23_STOP4[28]               - (W1S) Same as AC00_STOP0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP4_MASK                   0x10000000                // AC23_STOP4[28]
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP4_SHFT                   28
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP3_MASK                   0x08000000                // AC23_STOP3[27]
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP3_SHFT                   27
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP2_MASK                   0x04000000                // AC23_STOP2[26]
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP2_SHFT                   26
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP1_MASK                   0x02000000                // AC23_STOP1[25]
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP1_SHFT                   25
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP0_MASK                   0x01000000                // AC23_STOP0[24]
#define BN0_WF_ARB_TOP_TQPW2_AC23_STOP0_SHFT                   24
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP4_MASK                   0x00100000                // AC22_STOP4[20]
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP4_SHFT                   20
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP3_MASK                   0x00080000                // AC22_STOP3[19]
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP3_SHFT                   19
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP2_MASK                   0x00040000                // AC22_STOP2[18]
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP2_SHFT                   18
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP1_MASK                   0x00020000                // AC22_STOP1[17]
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP1_SHFT                   17
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP0_MASK                   0x00010000                // AC22_STOP0[16]
#define BN0_WF_ARB_TOP_TQPW2_AC22_STOP0_SHFT                   16
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP4_MASK                   0x00001000                // AC21_STOP4[12]
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP4_SHFT                   12
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP3_MASK                   0x00000800                // AC21_STOP3[11]
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP3_SHFT                   11
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP2_MASK                   0x00000400                // AC21_STOP2[10]
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP2_SHFT                   10
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP1_MASK                   0x00000200                // AC21_STOP1[9]
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP1_SHFT                   9
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP0_MASK                   0x00000100                // AC21_STOP0[8]
#define BN0_WF_ARB_TOP_TQPW2_AC21_STOP0_SHFT                   8
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP4_MASK                   0x00000010                // AC20_STOP4[4]
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP4_SHFT                   4
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP3_MASK                   0x00000008                // AC20_STOP3[3]
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP3_SHFT                   3
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP2_MASK                   0x00000004                // AC20_STOP2[2]
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP2_SHFT                   2
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP1_MASK                   0x00000002                // AC20_STOP1[1]
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP1_SHFT                   1
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW2_ADDR
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP0_MASK                   0x00000001                // AC20_STOP0[0]
#define BN0_WF_ARB_TOP_TQPW2_AC20_STOP0_SHFT                   0

/* =====================================================================================

  ---TQPW3 (0x820E3000 + 0x14C)---

    AC30_STOP0[0]                - (W1S) Same as AC00_STOP0~4
    AC30_STOP1[1]                - (W1S) Same as AC00_STOP0~4
    AC30_STOP2[2]                - (W1S) Same as AC00_STOP0~4
    AC30_STOP3[3]                - (W1S) Same as AC00_STOP0~4
    AC30_STOP4[4]                - (W1S) Same as AC00_STOP0~4
    RESERVED5[7..5]              - (RO) Reserved bits
    AC31_STOP0[8]                - (W1S) Same as AC00_STOP0~4
    AC31_STOP1[9]                - (W1S) Same as AC00_STOP0~4
    AC31_STOP2[10]               - (W1S) Same as AC00_STOP0~4
    AC31_STOP3[11]               - (W1S) Same as AC00_STOP0~4
    AC31_STOP4[12]               - (W1S) Same as AC00_STOP0~4
    RESERVED13[15..13]           - (RO) Reserved bits
    AC32_STOP0[16]               - (W1S) Same as AC00_STOP0~4
    AC32_STOP1[17]               - (W1S) Same as AC00_STOP0~4
    AC32_STOP2[18]               - (W1S) Same as AC00_STOP0~4
    AC32_STOP3[19]               - (W1S) Same as AC00_STOP0~4
    AC32_STOP4[20]               - (W1S) Same as AC00_STOP0~4
    RESERVED21[23..21]           - (RO) Reserved bits
    AC33_STOP0[24]               - (W1S) Same as AC00_STOP0~4
    AC33_STOP1[25]               - (W1S) Same as AC00_STOP0~4
    AC33_STOP2[26]               - (W1S) Same as AC00_STOP0~4
    AC33_STOP3[27]               - (W1S) Same as AC00_STOP0~4
    AC33_STOP4[28]               - (W1S) Same as AC00_STOP0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP4_MASK                   0x10000000                // AC33_STOP4[28]
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP4_SHFT                   28
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP3_MASK                   0x08000000                // AC33_STOP3[27]
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP3_SHFT                   27
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP2_MASK                   0x04000000                // AC33_STOP2[26]
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP2_SHFT                   26
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP1_MASK                   0x02000000                // AC33_STOP1[25]
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP1_SHFT                   25
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP0_MASK                   0x01000000                // AC33_STOP0[24]
#define BN0_WF_ARB_TOP_TQPW3_AC33_STOP0_SHFT                   24
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP4_MASK                   0x00100000                // AC32_STOP4[20]
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP4_SHFT                   20
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP3_MASK                   0x00080000                // AC32_STOP3[19]
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP3_SHFT                   19
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP2_MASK                   0x00040000                // AC32_STOP2[18]
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP2_SHFT                   18
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP1_MASK                   0x00020000                // AC32_STOP1[17]
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP1_SHFT                   17
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP0_MASK                   0x00010000                // AC32_STOP0[16]
#define BN0_WF_ARB_TOP_TQPW3_AC32_STOP0_SHFT                   16
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP4_MASK                   0x00001000                // AC31_STOP4[12]
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP4_SHFT                   12
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP3_MASK                   0x00000800                // AC31_STOP3[11]
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP3_SHFT                   11
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP2_MASK                   0x00000400                // AC31_STOP2[10]
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP2_SHFT                   10
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP1_MASK                   0x00000200                // AC31_STOP1[9]
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP1_SHFT                   9
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP0_MASK                   0x00000100                // AC31_STOP0[8]
#define BN0_WF_ARB_TOP_TQPW3_AC31_STOP0_SHFT                   8
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP4_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP4_MASK                   0x00000010                // AC30_STOP4[4]
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP4_SHFT                   4
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP3_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP3_MASK                   0x00000008                // AC30_STOP3[3]
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP3_SHFT                   3
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP2_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP2_MASK                   0x00000004                // AC30_STOP2[2]
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP2_SHFT                   2
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP1_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP1_MASK                   0x00000002                // AC30_STOP1[1]
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP1_SHFT                   1
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP0_ADDR                   BN0_WF_ARB_TOP_TQPW3_ADDR
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP0_MASK                   0x00000001                // AC30_STOP0[0]
#define BN0_WF_ARB_TOP_TQPW3_AC30_STOP0_SHFT                   0

/* =====================================================================================

  ---TQPM0 (0x820E3000 + 0x150)---

    ALTX0_STOP0[0]               - (W1S) Same as AC00_STOP0~4
    ALTX0_STOP1[1]               - (W1S) Same as AC00_STOP0~4
    ALTX0_STOP2[2]               - (W1S) Same as AC00_STOP0~4
    ALTX0_STOP3[3]               - (W1S) Same as AC00_STOP0~4
    ALTX0_STOP4[4]               - (W1S) Same as AC00_STOP0~4
    RESERVED5[23..5]             - (RO) Reserved bits
    PSMP0_STOP0[24]              - (W1S) Same as AC00_STOP0~4
    PSMP0_STOP1[25]              - (W1S) Same as AC00_STOP0~4
    PSMP0_STOP2[26]              - (W1S) Same as AC00_STOP0~4
    PSMP0_STOP3[27]              - (W1S) Same as AC00_STOP0~4
    PSMP0_STOP4[28]              - (W1S) Same as AC00_STOP0~4
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP4_ADDR                  BN0_WF_ARB_TOP_TQPM0_ADDR
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP4_MASK                  0x10000000                // PSMP0_STOP4[28]
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP4_SHFT                  28
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP3_ADDR                  BN0_WF_ARB_TOP_TQPM0_ADDR
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP3_MASK                  0x08000000                // PSMP0_STOP3[27]
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP3_SHFT                  27
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP2_ADDR                  BN0_WF_ARB_TOP_TQPM0_ADDR
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP2_MASK                  0x04000000                // PSMP0_STOP2[26]
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP2_SHFT                  26
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP1_ADDR                  BN0_WF_ARB_TOP_TQPM0_ADDR
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP1_MASK                  0x02000000                // PSMP0_STOP1[25]
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP1_SHFT                  25
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP0_ADDR                  BN0_WF_ARB_TOP_TQPM0_ADDR
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP0_MASK                  0x01000000                // PSMP0_STOP0[24]
#define BN0_WF_ARB_TOP_TQPM0_PSMP0_STOP0_SHFT                  24
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP4_ADDR                  BN0_WF_ARB_TOP_TQPM0_ADDR
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP4_MASK                  0x00000010                // ALTX0_STOP4[4]
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP4_SHFT                  4
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP3_ADDR                  BN0_WF_ARB_TOP_TQPM0_ADDR
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP3_MASK                  0x00000008                // ALTX0_STOP3[3]
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP3_SHFT                  3
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP2_ADDR                  BN0_WF_ARB_TOP_TQPM0_ADDR
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP2_MASK                  0x00000004                // ALTX0_STOP2[2]
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP2_SHFT                  2
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP1_ADDR                  BN0_WF_ARB_TOP_TQPM0_ADDR
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP1_MASK                  0x00000002                // ALTX0_STOP1[1]
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP1_SHFT                  1
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP0_ADDR                  BN0_WF_ARB_TOP_TQPM0_ADDR
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP0_MASK                  0x00000001                // ALTX0_STOP0[0]
#define BN0_WF_ARB_TOP_TQPM0_ALTX0_STOP0_SHFT                  0

/* =====================================================================================

  ---BTIMCR0 (0x820E3000 + 0x158)---

    BTIM_EN0_0[0]                - (RW) Start the TIM broadcast BSSID0_0 state machine. The DMA will load the start address from DMA.BCNQSAR to read the descriptor in SYSRAM and start the transmission.
                                     No flush and stop features, and only support trap.
                                     1: Enable TIM broadcast.
                                     0: Disable TIM broadcast.
                                     Both TIM broadcast and Beacon use BCN queue, the transmitted order depends on the en-queue order once both are active.
                                     The priority is BTIM = BCN > BMC
    BTIM_EN1[1]                  - (RW) The same as BTIM_EN0_0
    BTIM_EN2[2]                  - (RW) The same as BTIM_EN0_0
    BTIM_EN3[3]                  - (RW) The same as BTIM_EN0_0
    RESERVED4[16..4]             - (RO) Reserved bits
    BTIM_EN0_1[17]               - (RW) The same as BTIM_EN0_0
    BTIM_EN0_2[18]               - (RW) The same as BTIM_EN0_0
    BTIM_EN0_3[19]               - (RW) The same as BTIM_EN0_0
    BTIM_EN0_4[20]               - (RW) The same as BTIM_EN0_0
    BTIM_EN0_5[21]               - (RW) The same as BTIM_EN0_0
    BTIM_EN0_6[22]               - (RW) The same as BTIM_EN0_0
    BTIM_EN0_7[23]               - (RW) The same as BTIM_EN0_0
    BTIM_EN0_8[24]               - (RW) The same as BTIM_EN0_0
    BTIM_EN0_9[25]               - (RW) The same as BTIM_EN0_0
    BTIM_EN0_10[26]              - (RW) The same as BTIM_EN0_0
    BTIM_EN0_11[27]              - (RW) The same as BTIM_EN0_0
    BTIM_EN0_12[28]              - (RW) The same as BTIM_EN0_0
    BTIM_EN0_13[29]              - (RW) The same as BTIM_EN0_0
    BTIM_EN0_14[30]              - (RW) The same as BTIM_EN0_0
    BTIM_EN0_15[31]              - (RW) The same as BTIM_EN0_0

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_15_ADDR                BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_15_MASK                0x80000000                // BTIM_EN0_15[31]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_15_SHFT                31
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_14_ADDR                BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_14_MASK                0x40000000                // BTIM_EN0_14[30]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_14_SHFT                30
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_13_ADDR                BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_13_MASK                0x20000000                // BTIM_EN0_13[29]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_13_SHFT                29
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_12_ADDR                BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_12_MASK                0x10000000                // BTIM_EN0_12[28]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_12_SHFT                28
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_11_ADDR                BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_11_MASK                0x08000000                // BTIM_EN0_11[27]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_11_SHFT                27
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_10_ADDR                BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_10_MASK                0x04000000                // BTIM_EN0_10[26]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_10_SHFT                26
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_9_ADDR                 BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_9_MASK                 0x02000000                // BTIM_EN0_9[25]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_9_SHFT                 25
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_8_ADDR                 BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_8_MASK                 0x01000000                // BTIM_EN0_8[24]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_8_SHFT                 24
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_7_ADDR                 BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_7_MASK                 0x00800000                // BTIM_EN0_7[23]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_7_SHFT                 23
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_6_ADDR                 BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_6_MASK                 0x00400000                // BTIM_EN0_6[22]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_6_SHFT                 22
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_5_ADDR                 BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_5_MASK                 0x00200000                // BTIM_EN0_5[21]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_5_SHFT                 21
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_4_ADDR                 BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_4_MASK                 0x00100000                // BTIM_EN0_4[20]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_4_SHFT                 20
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_3_ADDR                 BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_3_MASK                 0x00080000                // BTIM_EN0_3[19]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_3_SHFT                 19
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_2_ADDR                 BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_2_MASK                 0x00040000                // BTIM_EN0_2[18]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_2_SHFT                 18
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_1_ADDR                 BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_1_MASK                 0x00020000                // BTIM_EN0_1[17]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_1_SHFT                 17
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN3_ADDR                   BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN3_MASK                   0x00000008                // BTIM_EN3[3]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN3_SHFT                   3
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN2_ADDR                   BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN2_MASK                   0x00000004                // BTIM_EN2[2]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN2_SHFT                   2
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN1_ADDR                   BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN1_MASK                   0x00000002                // BTIM_EN1[1]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN1_SHFT                   1
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_0_ADDR                 BN0_WF_ARB_TOP_BTIMCR0_ADDR
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_0_MASK                 0x00000001                // BTIM_EN0_0[0]
#define BN0_WF_ARB_TOP_BTIMCR0_BTIM_EN0_0_SHFT                 0

/* =====================================================================================

  ---BTIMCR1 (0x820E3000 + 0x15C)---

    BTIM_ECNT0_0[0]              - (RW) Indicate the number of TIM broadcast in this TTTT.
                                     1: means have 2 TIM broadcast.
                                     0: means have 1 TIM broadcast.
    BTIM_CNT1[1]                 - (RW) The same as BTIM_CNT0_0
    BTIM_CNT2[2]                 - (RW) The same as BTIM_CNT0_0
    BTIM_CNT3[3]                 - (RW) The same as BTIM_CNT0_0
    RESERVED4[16..4]             - (RO) Reserved bits
    BTIM_CNT0_1[17]              - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_2[18]              - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_3[19]              - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_4[20]              - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_5[21]              - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_6[22]              - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_7[23]              - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_8[24]              - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_9[25]              - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_10[26]             - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_11[27]             - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_12[28]             - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_13[29]             - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_14[30]             - (RW) The same as BTIM_CNT0_0
    BTIM_CNT0_15[31]             - (RW) The same as BTIM_CNT0_0

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_15_ADDR               BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_15_MASK               0x80000000                // BTIM_CNT0_15[31]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_15_SHFT               31
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_14_ADDR               BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_14_MASK               0x40000000                // BTIM_CNT0_14[30]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_14_SHFT               30
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_13_ADDR               BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_13_MASK               0x20000000                // BTIM_CNT0_13[29]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_13_SHFT               29
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_12_ADDR               BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_12_MASK               0x10000000                // BTIM_CNT0_12[28]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_12_SHFT               28
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_11_ADDR               BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_11_MASK               0x08000000                // BTIM_CNT0_11[27]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_11_SHFT               27
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_10_ADDR               BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_10_MASK               0x04000000                // BTIM_CNT0_10[26]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_10_SHFT               26
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_9_ADDR                BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_9_MASK                0x02000000                // BTIM_CNT0_9[25]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_9_SHFT                25
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_8_ADDR                BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_8_MASK                0x01000000                // BTIM_CNT0_8[24]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_8_SHFT                24
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_7_ADDR                BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_7_MASK                0x00800000                // BTIM_CNT0_7[23]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_7_SHFT                23
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_6_ADDR                BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_6_MASK                0x00400000                // BTIM_CNT0_6[22]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_6_SHFT                22
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_5_ADDR                BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_5_MASK                0x00200000                // BTIM_CNT0_5[21]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_5_SHFT                21
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_4_ADDR                BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_4_MASK                0x00100000                // BTIM_CNT0_4[20]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_4_SHFT                20
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_3_ADDR                BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_3_MASK                0x00080000                // BTIM_CNT0_3[19]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_3_SHFT                19
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_2_ADDR                BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_2_MASK                0x00040000                // BTIM_CNT0_2[18]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_2_SHFT                18
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_1_ADDR                BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_1_MASK                0x00020000                // BTIM_CNT0_1[17]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT0_1_SHFT                17
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT3_ADDR                  BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT3_MASK                  0x00000008                // BTIM_CNT3[3]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT3_SHFT                  3
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT2_ADDR                  BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT2_MASK                  0x00000004                // BTIM_CNT2[2]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT2_SHFT                  2
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT1_ADDR                  BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT1_MASK                  0x00000002                // BTIM_CNT1[1]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_CNT1_SHFT                  1
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_ECNT0_0_ADDR               BN0_WF_ARB_TOP_BTIMCR1_ADDR
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_ECNT0_0_MASK               0x00000001                // BTIM_ECNT0_0[0]
#define BN0_WF_ARB_TOP_BTIMCR1_BTIM_ECNT0_0_SHFT               0

/* =====================================================================================

  ---BMCCR0 (0x820E3000 + 0x160)---

    BMC_CNT0_0[7..0]             - (RW) The number of BMC BSSID0_0 in queue. It indicates the total current accumulated number of BMC packets. It will automatically add the written value and minus 1 once a BMC is transmitted done. The BMC queue backoff only when the corresponding BMC_CNT is not equal to zero.
    BMC_CNT1[15..8]              - (RW) The same as BMC_CNT0_0
    BMC_CNT2[23..16]             - (RW) The same as BMC_CNT0_0
    BMC_CNT3[31..24]             - (RW) The same as BMC_CNT0_0

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT3_ADDR                    BN0_WF_ARB_TOP_BMCCR0_ADDR
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT3_MASK                    0xFF000000                // BMC_CNT3[31..24]
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT3_SHFT                    24
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT2_ADDR                    BN0_WF_ARB_TOP_BMCCR0_ADDR
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT2_MASK                    0x00FF0000                // BMC_CNT2[23..16]
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT2_SHFT                    16
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT1_ADDR                    BN0_WF_ARB_TOP_BMCCR0_ADDR
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT1_MASK                    0x0000FF00                // BMC_CNT1[15..8]
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT1_SHFT                    8
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT0_0_ADDR                  BN0_WF_ARB_TOP_BMCCR0_ADDR
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT0_0_MASK                  0x000000FF                // BMC_CNT0_0[7..0]
#define BN0_WF_ARB_TOP_BMCCR0_BMC_CNT0_0_SHFT                  0

/* =====================================================================================

  ---BMCCR1 (0x820E3000 + 0x164)---

    BMC_CNT0_1[7..0]             - (RW) The same as BMC_CNT0_0
    BMC_CNT0_2[15..8]            - (RW) The same as BMC_CNT0_0
    BMC_CNT0_3[23..16]           - (RW) The same as BMC_CNT0_0
    BMC_CNT0_4[31..24]           - (RW) The same as BMC_CNT0_0

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_4_ADDR                  BN0_WF_ARB_TOP_BMCCR1_ADDR
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_4_MASK                  0xFF000000                // BMC_CNT0_4[31..24]
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_4_SHFT                  24
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_3_ADDR                  BN0_WF_ARB_TOP_BMCCR1_ADDR
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_3_MASK                  0x00FF0000                // BMC_CNT0_3[23..16]
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_3_SHFT                  16
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_2_ADDR                  BN0_WF_ARB_TOP_BMCCR1_ADDR
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_2_MASK                  0x0000FF00                // BMC_CNT0_2[15..8]
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_2_SHFT                  8
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_1_ADDR                  BN0_WF_ARB_TOP_BMCCR1_ADDR
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_1_MASK                  0x000000FF                // BMC_CNT0_1[7..0]
#define BN0_WF_ARB_TOP_BMCCR1_BMC_CNT0_1_SHFT                  0

/* =====================================================================================

  ---BMCCR2 (0x820E3000 + 0x168)---

    BMC_CNT0_5[7..0]             - (RW) The same as BMC_CNT0_0
    BMC_CNT0_6[15..8]            - (RW) The same as BMC_CNT0_0
    BMC_CNT0_7[23..16]           - (RW) The same as BMC_CNT0_0
    BMC_CNT0_8[31..24]           - (RW) The same as BMC_CNT0_0

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_8_ADDR                  BN0_WF_ARB_TOP_BMCCR2_ADDR
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_8_MASK                  0xFF000000                // BMC_CNT0_8[31..24]
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_8_SHFT                  24
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_7_ADDR                  BN0_WF_ARB_TOP_BMCCR2_ADDR
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_7_MASK                  0x00FF0000                // BMC_CNT0_7[23..16]
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_7_SHFT                  16
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_6_ADDR                  BN0_WF_ARB_TOP_BMCCR2_ADDR
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_6_MASK                  0x0000FF00                // BMC_CNT0_6[15..8]
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_6_SHFT                  8
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_5_ADDR                  BN0_WF_ARB_TOP_BMCCR2_ADDR
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_5_MASK                  0x000000FF                // BMC_CNT0_5[7..0]
#define BN0_WF_ARB_TOP_BMCCR2_BMC_CNT0_5_SHFT                  0

/* =====================================================================================

  ---BMCCR3 (0x820E3000 + 0x16C)---

    BMC_CNT0_9[7..0]             - (RW) The same as BMC_CNT0_0
    BMC_CNT0_10[15..8]           - (RW) The same as BMC_CNT0_0
    BMC_CNT0_11[23..16]          - (RW) The same as BMC_CNT0_0
    BMC_CNT0_12[31..24]          - (RW) The same as BMC_CNT0_0

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_12_ADDR                 BN0_WF_ARB_TOP_BMCCR3_ADDR
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_12_MASK                 0xFF000000                // BMC_CNT0_12[31..24]
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_12_SHFT                 24
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_11_ADDR                 BN0_WF_ARB_TOP_BMCCR3_ADDR
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_11_MASK                 0x00FF0000                // BMC_CNT0_11[23..16]
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_11_SHFT                 16
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_10_ADDR                 BN0_WF_ARB_TOP_BMCCR3_ADDR
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_10_MASK                 0x0000FF00                // BMC_CNT0_10[15..8]
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_10_SHFT                 8
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_9_ADDR                  BN0_WF_ARB_TOP_BMCCR3_ADDR
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_9_MASK                  0x000000FF                // BMC_CNT0_9[7..0]
#define BN0_WF_ARB_TOP_BMCCR3_BMC_CNT0_9_SHFT                  0

/* =====================================================================================

  ---BMCCR4 (0x820E3000 + 0x170)---

    BMC_CNT0_13[7..0]            - (RW) The same as BMC_CNT0_0
    BMC_CNT0_14[15..8]           - (RW) The same as BMC_CNT0_0
    BMC_CNT0_15[23..16]          - (RW) The same as BMC_CNT0_0
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BMCCR4_BMC_CNT0_15_ADDR                 BN0_WF_ARB_TOP_BMCCR4_ADDR
#define BN0_WF_ARB_TOP_BMCCR4_BMC_CNT0_15_MASK                 0x00FF0000                // BMC_CNT0_15[23..16]
#define BN0_WF_ARB_TOP_BMCCR4_BMC_CNT0_15_SHFT                 16
#define BN0_WF_ARB_TOP_BMCCR4_BMC_CNT0_14_ADDR                 BN0_WF_ARB_TOP_BMCCR4_ADDR
#define BN0_WF_ARB_TOP_BMCCR4_BMC_CNT0_14_MASK                 0x0000FF00                // BMC_CNT0_14[15..8]
#define BN0_WF_ARB_TOP_BMCCR4_BMC_CNT0_14_SHFT                 8
#define BN0_WF_ARB_TOP_BMCCR4_BMC_CNT0_13_ADDR                 BN0_WF_ARB_TOP_BMCCR4_ADDR
#define BN0_WF_ARB_TOP_BMCCR4_BMC_CNT0_13_MASK                 0x000000FF                // BMC_CNT0_13[7..0]
#define BN0_WF_ARB_TOP_BMCCR4_BMC_CNT0_13_SHFT                 0

/* =====================================================================================

  ---BMCCR5 (0x820E3000 + 0x174)---

    BMC_CNT_CLR0_0[0]            - (W1C) Write 1 to clear the value of BMC_CNT0_0 to zero. Write 0 is meaningless.
    BMC_CNT_CLR1[1]              - (W1C) Write 1 to clear the value of BMC_CNT1 to zero. Write 0 is meaningless.
    BMC_CNT_CLR2[2]              - (W1C) Write 1 to clear the value of BMC_CNT2 to zero. Write 0 is meaningless.
    BMC_CNT_CLR3[3]              - (W1C) Write 1 to clear the value of BMC_CNT3 to zero. Write 0 is meaningless.
    RESERVED4[16..4]             - (RO) Reserved bits
    BMC_CNT_CLR0_1[17]           - (W1C) Write 1 to clear the value of BMC_CNT0_1 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_2[18]           - (W1C) Write 1 to clear the value of BMC_CNT0_2 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_3[19]           - (W1C) Write 1 to clear the value of BMC_CNT0_3 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_4[20]           - (W1C) Write 1 to clear the value of BMC_CNT0_4 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_5[21]           - (W1C) Write 1 to clear the value of BMC_CNT0_5 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_6[22]           - (W1C) Write 1 to clear the value of BMC_CNT0_6 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_7[23]           - (W1C) Write 1 to clear the value of BMC_CNT0_7 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_8[24]           - (W1C) Write 1 to clear the value of BMC_CNT0_8 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_9[25]           - (W1C) Write 1 to clear the value of BMC_CNT0_9 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_10[26]          - (W1C) Write 1 to clear the value of BMC_CNT0_10 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_11[27]          - (W1C) Write 1 to clear the value of BMC_CNT0_11 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_12[28]          - (W1C) Write 1 to clear the value of BMC_CNT0_12 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_13[29]          - (W1C) Write 1 to clear the value of BMC_CNT0_13 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_14[30]          - (W1C) Write 1 to clear the value of BMC_CNT0_14 to zero. Write 0 is meaningless.
    BMC_CNT_CLR0_15[31]          - (W1C) Write 1 to clear the value of BMC_CNT0_15 to zero. Write 0 is meaningless.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_15_ADDR             BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_15_MASK             0x80000000                // BMC_CNT_CLR0_15[31]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_15_SHFT             31
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_14_ADDR             BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_14_MASK             0x40000000                // BMC_CNT_CLR0_14[30]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_14_SHFT             30
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_13_ADDR             BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_13_MASK             0x20000000                // BMC_CNT_CLR0_13[29]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_13_SHFT             29
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_12_ADDR             BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_12_MASK             0x10000000                // BMC_CNT_CLR0_12[28]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_12_SHFT             28
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_11_ADDR             BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_11_MASK             0x08000000                // BMC_CNT_CLR0_11[27]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_11_SHFT             27
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_10_ADDR             BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_10_MASK             0x04000000                // BMC_CNT_CLR0_10[26]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_10_SHFT             26
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_9_ADDR              BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_9_MASK              0x02000000                // BMC_CNT_CLR0_9[25]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_9_SHFT              25
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_8_ADDR              BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_8_MASK              0x01000000                // BMC_CNT_CLR0_8[24]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_8_SHFT              24
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_7_ADDR              BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_7_MASK              0x00800000                // BMC_CNT_CLR0_7[23]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_7_SHFT              23
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_6_ADDR              BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_6_MASK              0x00400000                // BMC_CNT_CLR0_6[22]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_6_SHFT              22
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_5_ADDR              BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_5_MASK              0x00200000                // BMC_CNT_CLR0_5[21]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_5_SHFT              21
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_4_ADDR              BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_4_MASK              0x00100000                // BMC_CNT_CLR0_4[20]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_4_SHFT              20
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_3_ADDR              BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_3_MASK              0x00080000                // BMC_CNT_CLR0_3[19]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_3_SHFT              19
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_2_ADDR              BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_2_MASK              0x00040000                // BMC_CNT_CLR0_2[18]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_2_SHFT              18
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_1_ADDR              BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_1_MASK              0x00020000                // BMC_CNT_CLR0_1[17]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_1_SHFT              17
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR3_ADDR                BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR3_MASK                0x00000008                // BMC_CNT_CLR3[3]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR3_SHFT                3
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR2_ADDR                BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR2_MASK                0x00000004                // BMC_CNT_CLR2[2]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR2_SHFT                2
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR1_ADDR                BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR1_MASK                0x00000002                // BMC_CNT_CLR1[1]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR1_SHFT                1
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_0_ADDR              BN0_WF_ARB_TOP_BMCCR5_ADDR
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_0_MASK              0x00000001                // BMC_CNT_CLR0_0[0]
#define BN0_WF_ARB_TOP_BMCCR5_BMC_CNT_CLR0_0_SHFT              0

/* =====================================================================================

  ---GTQR0 (0x820E3000 + 0x178)---

    GUARD_TIME_AC00[7..0]        - (RW) In unit of 64 us. This guard time is used when AC00 received stop command while transmitting one packet. HW MAC would not stop this packet until timeout of guard time
    GUARD_TIME_AC01[15..8]       - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC02[23..16]      - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC03[31..24]      - (RW) The same as GUARD_TIME_AC00.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC03_ADDR              BN0_WF_ARB_TOP_GTQR0_ADDR
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC03_MASK              0xFF000000                // GUARD_TIME_AC03[31..24]
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC03_SHFT              24
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC02_ADDR              BN0_WF_ARB_TOP_GTQR0_ADDR
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC02_MASK              0x00FF0000                // GUARD_TIME_AC02[23..16]
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC02_SHFT              16
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC01_ADDR              BN0_WF_ARB_TOP_GTQR0_ADDR
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC01_MASK              0x0000FF00                // GUARD_TIME_AC01[15..8]
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC01_SHFT              8
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC00_ADDR              BN0_WF_ARB_TOP_GTQR0_ADDR
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC00_MASK              0x000000FF                // GUARD_TIME_AC00[7..0]
#define BN0_WF_ARB_TOP_GTQR0_GUARD_TIME_AC00_SHFT              0

/* =====================================================================================

  ---GTQR1 (0x820E3000 + 0x17C)---

    GUARD_TIME_AC10[7..0]        - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC11[15..8]       - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC12[23..16]      - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC13[31..24]      - (RW) The same as GUARD_TIME_AC00.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC13_ADDR              BN0_WF_ARB_TOP_GTQR1_ADDR
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC13_MASK              0xFF000000                // GUARD_TIME_AC13[31..24]
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC13_SHFT              24
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC12_ADDR              BN0_WF_ARB_TOP_GTQR1_ADDR
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC12_MASK              0x00FF0000                // GUARD_TIME_AC12[23..16]
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC12_SHFT              16
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC11_ADDR              BN0_WF_ARB_TOP_GTQR1_ADDR
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC11_MASK              0x0000FF00                // GUARD_TIME_AC11[15..8]
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC11_SHFT              8
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC10_ADDR              BN0_WF_ARB_TOP_GTQR1_ADDR
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC10_MASK              0x000000FF                // GUARD_TIME_AC10[7..0]
#define BN0_WF_ARB_TOP_GTQR1_GUARD_TIME_AC10_SHFT              0

/* =====================================================================================

  ---GTQR2 (0x820E3000 + 0x180)---

    GUARD_TIME_AC20[7..0]        - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC21[15..8]       - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC22[23..16]      - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC23[31..24]      - (RW) The same as GUARD_TIME_AC00.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC23_ADDR              BN0_WF_ARB_TOP_GTQR2_ADDR
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC23_MASK              0xFF000000                // GUARD_TIME_AC23[31..24]
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC23_SHFT              24
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC22_ADDR              BN0_WF_ARB_TOP_GTQR2_ADDR
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC22_MASK              0x00FF0000                // GUARD_TIME_AC22[23..16]
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC22_SHFT              16
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC21_ADDR              BN0_WF_ARB_TOP_GTQR2_ADDR
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC21_MASK              0x0000FF00                // GUARD_TIME_AC21[15..8]
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC21_SHFT              8
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC20_ADDR              BN0_WF_ARB_TOP_GTQR2_ADDR
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC20_MASK              0x000000FF                // GUARD_TIME_AC20[7..0]
#define BN0_WF_ARB_TOP_GTQR2_GUARD_TIME_AC20_SHFT              0

/* =====================================================================================

  ---GTQR3 (0x820E3000 + 0x184)---

    GUARD_TIME_AC30[7..0]        - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC31[15..8]       - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC32[23..16]      - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_AC33[31..24]      - (RW) The same as GUARD_TIME_AC00.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC33_ADDR              BN0_WF_ARB_TOP_GTQR3_ADDR
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC33_MASK              0xFF000000                // GUARD_TIME_AC33[31..24]
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC33_SHFT              24
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC32_ADDR              BN0_WF_ARB_TOP_GTQR3_ADDR
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC32_MASK              0x00FF0000                // GUARD_TIME_AC32[23..16]
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC32_SHFT              16
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC31_ADDR              BN0_WF_ARB_TOP_GTQR3_ADDR
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC31_MASK              0x0000FF00                // GUARD_TIME_AC31[15..8]
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC31_SHFT              8
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC30_ADDR              BN0_WF_ARB_TOP_GTQR3_ADDR
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC30_MASK              0x000000FF                // GUARD_TIME_AC30[7..0]
#define BN0_WF_ARB_TOP_GTQR3_GUARD_TIME_AC30_SHFT              0

/* =====================================================================================

  ---GTQR4 (0x820E3000 + 0x188)---

    GUARD_TIME_ALTX0[7..0]       - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_BMC0[15..8]       - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_BCN0[23..16]      - (RW) The same as GUARD_TIME_AC00.
    GUARD_TIME_PSMP0[31..24]     - (RW) The same as GUARD_TIME_AC00.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_PSMP0_ADDR             BN0_WF_ARB_TOP_GTQR4_ADDR
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_PSMP0_MASK             0xFF000000                // GUARD_TIME_PSMP0[31..24]
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_PSMP0_SHFT             24
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_BCN0_ADDR              BN0_WF_ARB_TOP_GTQR4_ADDR
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_BCN0_MASK              0x00FF0000                // GUARD_TIME_BCN0[23..16]
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_BCN0_SHFT              16
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_BMC0_ADDR              BN0_WF_ARB_TOP_GTQR4_ADDR
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_BMC0_MASK              0x0000FF00                // GUARD_TIME_BMC0[15..8]
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_BMC0_SHFT              8
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_ALTX0_ADDR             BN0_WF_ARB_TOP_GTQR4_ADDR
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_ALTX0_MASK             0x000000FF                // GUARD_TIME_ALTX0[7..0]
#define BN0_WF_ARB_TOP_GTQR4_GUARD_TIME_ALTX0_SHFT             0

/* =====================================================================================

  ---BFCR (0x820E3000 + 0x190)---

    LAST_PPDU_PDICT0[0]          - (RW) LAST PPDU prediction or not. Normally, the AIFS/BFN reload at air end. However, for prediction mode, the AIFS/BFN reload at TXOP start.
                                     0: AIFS/BFN reload at air end.
                                     1: AIFS/BFN reload at TXOP start.
                                     For DBDC channel 0
    BACK_OFF_CTRL0[1]            - (RW) Back off control:
                                         FW set this bit to 1 to re-backoff the BFN counter at air end if its BFN has reached zero
                                     0: If the queue's  corresponding BFN is zero, keep zero when air end.
                                     1: If the queue's corresponding BFN is zero, re-backoff the BFN counter at air end.
                                     For DBDC channel 0
    PRI_CTL0[2]                  - (RW) When internal collision, this bit is used to control the priority between AC00~AC33 (if queue is in DBDC channel0).
                                     0: AC03 > AC13 > AC23 > AC33 >
                                         AC02 > AC12 > AC22 > AC32 >
                                         AC01 > AC11 > AC21 > AC31 >
                                         AC00 > AC10 > AC20 > AC30
                                     1: AC03 > AC02 > AC01 > AC00 >
                                         AC13 > AC12 > AC11 > AC10 >
                                         AC23 > AC22 > AC21 > AC20 >
                                         AC33 > AC32 > AC31 > AC30
                                     For DBDC channel 0
    CW_CTL0[3]                   - (RW) This bit is used for the internal contention
                                     1: contention window will be enlarged when internal contention occurs
                                     0: contention window will not be enlarged when internal contention occurs
                                     For DBDC channel 0
    MIN_IFSBFN[7..4]             - (RW) Minimum interframe space + backoff number
                                     After IFS reload, if current AIFS+BNF < MIN_BFN, ARB will force IFS = MIN_IFS - BFN (to make sure IFS+BFN >= MIN_IFS)
                                     EARLY_BFTO must >= MIN_IFSBFN
    TMAC0_MNG_SLOT_IDLE[8]       - (RO) It will toggle when there was a tmac0_mng_slot_idle occurs.
                                     For DBDC channel 0
    AGG0_TX_END_TOGGLE[9]        - (RO) It will toggle when there was a agg0_tx_end occurs.
                                     For DBDC channel 0
    LP0_PRETTTT_TOGGLE[10]       - (RO) It will toggle when there was a lp_pretttt_pu occurs.
                                     For DBDC channel 0
    LP0_TTTT_TOGGLE[11]          - (RO) It will toggle when there was a lp_txbtim_start occurs.
                                     For DBDC channel 0
    LP0_PRETBTT_TOGGLE[12]       - (RO) It will toggle when there was a lp_pretbtt_pu occurs.
                                     For DBDC channel 0
    LP0_TBTT_TOGGLE[13]          - (RO) It will toggle when there was a lp_txbcn_start occurs.
                                     For DBDC channel 0
    TMAC0_SLOT_IDLE_TOGGLE[14]   - (RO) It will toggle when there was a tmac0_pu_slot_idle occurs.
                                     For DBDC channel 0
    ARB0_TX_START_TOGGLE[15]     - (RO) will toggle when there was a arb0_tx_start occurs.
                                     For DBDC channel 0
    RESERVED16[19..16]           - (RO) Reserved bits
    EARLY_BFTO[23..20]           - (RW) Early backoff timeout
                                     ARB will early backoff timeout for
                                     1. PLE select queue (by airtime fairness or bandwidth control)
                                     2. MU grouping select
                                     3. AGG aggregation
                                     4. PSE pre-download data for cut-throughput
                                     EARLY_BFTO must >= MIN_IFSBFN
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_BFCR_EARLY_BFTO_ADDR                    BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_EARLY_BFTO_MASK                    0x00F00000                // EARLY_BFTO[23..20]
#define BN0_WF_ARB_TOP_BFCR_EARLY_BFTO_SHFT                    20
#define BN0_WF_ARB_TOP_BFCR_ARB0_TX_START_TOGGLE_ADDR          BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_ARB0_TX_START_TOGGLE_MASK          0x00008000                // ARB0_TX_START_TOGGLE[15]
#define BN0_WF_ARB_TOP_BFCR_ARB0_TX_START_TOGGLE_SHFT          15
#define BN0_WF_ARB_TOP_BFCR_TMAC0_SLOT_IDLE_TOGGLE_ADDR        BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_TMAC0_SLOT_IDLE_TOGGLE_MASK        0x00004000                // TMAC0_SLOT_IDLE_TOGGLE[14]
#define BN0_WF_ARB_TOP_BFCR_TMAC0_SLOT_IDLE_TOGGLE_SHFT        14
#define BN0_WF_ARB_TOP_BFCR_LP0_TBTT_TOGGLE_ADDR               BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_LP0_TBTT_TOGGLE_MASK               0x00002000                // LP0_TBTT_TOGGLE[13]
#define BN0_WF_ARB_TOP_BFCR_LP0_TBTT_TOGGLE_SHFT               13
#define BN0_WF_ARB_TOP_BFCR_LP0_PRETBTT_TOGGLE_ADDR            BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_LP0_PRETBTT_TOGGLE_MASK            0x00001000                // LP0_PRETBTT_TOGGLE[12]
#define BN0_WF_ARB_TOP_BFCR_LP0_PRETBTT_TOGGLE_SHFT            12
#define BN0_WF_ARB_TOP_BFCR_LP0_TTTT_TOGGLE_ADDR               BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_LP0_TTTT_TOGGLE_MASK               0x00000800                // LP0_TTTT_TOGGLE[11]
#define BN0_WF_ARB_TOP_BFCR_LP0_TTTT_TOGGLE_SHFT               11
#define BN0_WF_ARB_TOP_BFCR_LP0_PRETTTT_TOGGLE_ADDR            BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_LP0_PRETTTT_TOGGLE_MASK            0x00000400                // LP0_PRETTTT_TOGGLE[10]
#define BN0_WF_ARB_TOP_BFCR_LP0_PRETTTT_TOGGLE_SHFT            10
#define BN0_WF_ARB_TOP_BFCR_AGG0_TX_END_TOGGLE_ADDR            BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_AGG0_TX_END_TOGGLE_MASK            0x00000200                // AGG0_TX_END_TOGGLE[9]
#define BN0_WF_ARB_TOP_BFCR_AGG0_TX_END_TOGGLE_SHFT            9
#define BN0_WF_ARB_TOP_BFCR_TMAC0_MNG_SLOT_IDLE_ADDR           BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_TMAC0_MNG_SLOT_IDLE_MASK           0x00000100                // TMAC0_MNG_SLOT_IDLE[8]
#define BN0_WF_ARB_TOP_BFCR_TMAC0_MNG_SLOT_IDLE_SHFT           8
#define BN0_WF_ARB_TOP_BFCR_MIN_IFSBFN_ADDR                    BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_MIN_IFSBFN_MASK                    0x000000F0                // MIN_IFSBFN[7..4]
#define BN0_WF_ARB_TOP_BFCR_MIN_IFSBFN_SHFT                    4
#define BN0_WF_ARB_TOP_BFCR_CW_CTL0_ADDR                       BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_CW_CTL0_MASK                       0x00000008                // CW_CTL0[3]
#define BN0_WF_ARB_TOP_BFCR_CW_CTL0_SHFT                       3
#define BN0_WF_ARB_TOP_BFCR_PRI_CTL0_ADDR                      BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_PRI_CTL0_MASK                      0x00000004                // PRI_CTL0[2]
#define BN0_WF_ARB_TOP_BFCR_PRI_CTL0_SHFT                      2
#define BN0_WF_ARB_TOP_BFCR_BACK_OFF_CTRL0_ADDR                BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_BACK_OFF_CTRL0_MASK                0x00000002                // BACK_OFF_CTRL0[1]
#define BN0_WF_ARB_TOP_BFCR_BACK_OFF_CTRL0_SHFT                1
#define BN0_WF_ARB_TOP_BFCR_LAST_PPDU_PDICT0_ADDR              BN0_WF_ARB_TOP_BFCR_ADDR
#define BN0_WF_ARB_TOP_BFCR_LAST_PPDU_PDICT0_MASK              0x00000001                // LAST_PPDU_PDICT0[0]
#define BN0_WF_ARB_TOP_BFCR_LAST_PPDU_PDICT0_SHFT              0

/* =====================================================================================

  ---DRNGR0 (0x820E3000 + 0x194)---

    PRNG0[15..0]                 - (RW) Pseudo Random Number Generator 0
                                     When write, the value will be programmed to the content of the 16-bit shift registers in the pseudo random number generator of.
                                     Fibonacci LFSRs: X^16 + X^15 + X^14 + X5 + 1.
                                     
                                     Current HW, each AC's random number use PRNG0 bit as follow
                                       AC00:  {{F.E,D,C}, {B,A,9,8}, {7,6,5,4}, {3,2,1,0}}
                                       AC01:  {{7,6,5,4}, {3,2,1,0}, {F.E,D,C}, {B,A,9,8}}
                                       AC02:  {{3,2,1,0}, {7,6,5,4}, {B,A,9,8}, {F.E,D,C}}
                                       AC03:  {{B,A,9,8}, {F.E,D,C}, {3,2,1,0}, {7,6,5,4}}
                                       AC20:  {{C,D,E,F}, {8,9,A,B}, {4,5,6,7}, {0,1,2,3}}
                                       AC21:  {{4,5,6,7}, {0,1,2,3}, {C,D,E,F}, {8,9,A,B}}
                                       AC22:  {{0,1,2,3}, {4,5,6,7}, {8,9,A,B}, {C,D,E,F}}
                                       AC23:  {{8,9,A,B}, {C,D,E,F}, {0,1,2,3}, {4,5,6,7}}
                                       ALTX0: {{E,F,C,D}, {A,B,8,9}, {6,7,4,5}, {2,3,0,1}}
                                       BMC0: {{2,3,0,1}, {6,7,4,5}, {A,B,8,9}, {E,F,C,D}}
                                       BCN0: {{A,B,8,9}, {E,F,C,D}, {2,3,0,1}, {6,7,4,5}}
                                       NAF:   {{5,4,7,6}, {1,0,3,2}, {D,C,F,E}, {9,8,B,A}}
                                       NBCN: {{1,0,3,2}, {5,4,7,6}, {9,8,B,A}, {D,C,F,E}}
                                       RWP0:  {{D,C,F,E}, {9,8,B,A}, {5,4,7,6}, {1,0,3,2}}
    PRNG0_FIXED[16]              - (RW) This bit is used to control the free run function of pseudorandom number generator. Software driver should write Fixed bit first to stop the free run of the pseudo random number generator, and then write data to PRNG0.
                                     0: free run
                                     1: fixed to PRNG0.
    RESERVED17[31..17]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_DRNGR0_PRNG0_FIXED_ADDR                 BN0_WF_ARB_TOP_DRNGR0_ADDR
#define BN0_WF_ARB_TOP_DRNGR0_PRNG0_FIXED_MASK                 0x00010000                // PRNG0_FIXED[16]
#define BN0_WF_ARB_TOP_DRNGR0_PRNG0_FIXED_SHFT                 16
#define BN0_WF_ARB_TOP_DRNGR0_PRNG0_ADDR                       BN0_WF_ARB_TOP_DRNGR0_ADDR
#define BN0_WF_ARB_TOP_DRNGR0_PRNG0_MASK                       0x0000FFFF                // PRNG0[15..0]
#define BN0_WF_ARB_TOP_DRNGR0_PRNG0_SHFT                       0

/* =====================================================================================

  ---DRNGR1 (0x820E3000 + 0x198)---

    PRNG1[15..0]                 - (RW) Pseudo Random Number Generator 1
                                     When write, the value will be programmed to the content of the 16-bit shift registers in the pseudo random number generator of 
                                     Fibonacci LFSRs: X^16 + X^14 + X^13 + X11 + 1.
                                     
                                     Current HW, each AC's random number use PRNG1 bit as follow
                                       AC10:  {{F.E,D,C}, {B,A,9,8}, {7,6,5,4}, {3,2,1,0}}
                                       AC11:  {{7,6,5,4}, {3,2,1,0}, {F.E,D,C}, {B,A,9,8}}
                                       AC12:  {{3,2,1,0}, {7,6,5,4}, {B,A,9,8}, {F.E,D,C}}
                                       AC13:  {{B,A,9,8}, {F.E,D,C}, {3,2,1,0}, {7,6,5,4}}
                                       AC30:  {{C,D,E,F}, {8,9,A,B}, {4,5,6,7}, {0,1,2,3}}
                                       AC31:  {{4,5,6,7}, {0,1,2,3}, {C,D,E,F}, {8,9,A,B}}
                                       AC32:  {{0,1,2,3}, {4,5,6,7}, {8,9,A,B}, {C,D,E,F}}
                                       AC33:  {{8,9,A,B}, {C,D,E,F}, {0,1,2,3}, {4,5,6,7}}
                                       ALTX1: {{E,F,C,D}, {A,B,8,9}, {6,7,4,5}, {2,3,0,1}}
                                       BMC1: {{2,3,0,1}, {6,7,4,5}, {A,B,8,9}, {E,F,C,D}}
                                       BCN1: {{A,B,8,9}, {E,F,C,D}, {2,3,0,1}, {6,7,4,5}}
                                       RWP1:  {{D,C,F,E}, {9,8,B,A}, {5,4,7,6}, {1,0,3,2}}
    PRNG1_FIXED[16]              - (RW) This bit is used to control the free run function of pseudorandom number generator. Software driver should write Fixed bit first to stop the free run of the pseudo random number generator, and then write data to PRNG1.
                                     0: free run
                                     1: fixed to PRNG1.
    RESERVED17[31..17]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_DRNGR1_PRNG1_FIXED_ADDR                 BN0_WF_ARB_TOP_DRNGR1_ADDR
#define BN0_WF_ARB_TOP_DRNGR1_PRNG1_FIXED_MASK                 0x00010000                // PRNG1_FIXED[16]
#define BN0_WF_ARB_TOP_DRNGR1_PRNG1_FIXED_SHFT                 16
#define BN0_WF_ARB_TOP_DRNGR1_PRNG1_ADDR                       BN0_WF_ARB_TOP_DRNGR1_ADDR
#define BN0_WF_ARB_TOP_DRNGR1_PRNG1_MASK                       0x0000FFFF                // PRNG1[15..0]
#define BN0_WF_ARB_TOP_DRNGR1_PRNG1_SHFT                       0

/* =====================================================================================

  ---TXENTRYR (0x820E3000 + 0x19C)---

    TX_ENTRY_MODE[0]             - (RW) The switch of using entry mode to abort or not.
                                     1: Enable. The transmitted packet will be aborted if the entry address of this packet is matched to arb_cr_tx_entry_addr when stop and flush occurs. But the arb_cr_ac*_en will not disable.
                                     0: Disable.
    RESERVED1[7..1]              - (RO) Reserved bits
    TX_ENTRY_ADDR[15..8]         - (RW) The entry address of the to-be-aborted packet.
                                     The switch of using entry mode to abort or not.
                                     1: Enable. The transmitted packet will be aborted if the entry address of this packet is matched to arb_cr_tx_entry_addr when stop and flush occurs. But the arb_cr_ac*_en will not disable.
                                     0: Disable.
    RESERVED16[30..16]           - (RO) Reserved bits
    TMAC_ALWAYS_ABORT[31]        - (RW) TMAC always abort.
                                      0: TMAC abort will ignore if Tx is idle.
                                      1: TMAC abort will execute even Tx is idle.

 =====================================================================================*/
#define BN0_WF_ARB_TOP_TXENTRYR_TMAC_ALWAYS_ABORT_ADDR         BN0_WF_ARB_TOP_TXENTRYR_ADDR
#define BN0_WF_ARB_TOP_TXENTRYR_TMAC_ALWAYS_ABORT_MASK         0x80000000                // TMAC_ALWAYS_ABORT[31]
#define BN0_WF_ARB_TOP_TXENTRYR_TMAC_ALWAYS_ABORT_SHFT         31
#define BN0_WF_ARB_TOP_TXENTRYR_TX_ENTRY_ADDR_ADDR             BN0_WF_ARB_TOP_TXENTRYR_ADDR
#define BN0_WF_ARB_TOP_TXENTRYR_TX_ENTRY_ADDR_MASK             0x0000FF00                // TX_ENTRY_ADDR[15..8]
#define BN0_WF_ARB_TOP_TXENTRYR_TX_ENTRY_ADDR_SHFT             8
#define BN0_WF_ARB_TOP_TXENTRYR_TX_ENTRY_MODE_ADDR             BN0_WF_ARB_TOP_TXENTRYR_ADDR
#define BN0_WF_ARB_TOP_TXENTRYR_TX_ENTRY_MODE_MASK             0x00000001                // TX_ENTRY_MODE[0]
#define BN0_WF_ARB_TOP_TXENTRYR_TX_ENTRY_MODE_SHFT             0

/* =====================================================================================

  ---WMMAC00 (0x820E3000 + 0x1A0)---

    AIFS_AC00[3..0]              - (RW) The AIFS for AC00 in unit of slot time minus one SIFS time. 0 is not allowed, and 1 only allowed in AP mode.
                                     If want to change AIFS, user should stop the corresponding queue and set the new AIFS value and then need to start again.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC00[12..8]            - (RW) The minimum contention window in unit of slot for AC00. The value shall be set to (2^n - 1).
                                      0: means CW minimum is 16'b0000_0000_0000_0000
                                      1: means CW minimum is 16'b0000_0000_0000_0001
                                      2: means CW minimum is 16'b0000_0000_0000_0011
                                      ...
                                      n: means CW minimum is (2^n - 1)
                                      ...
                                     16: means CW minimum is 16'b1111_1111_1111_1111
                                     17~31: reserved
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC00[20..16]           - (RW) The maximum contention window in unit of slot for AC00. The value shall be set to (2^n - 1).
                                     0: means CW maximum is 16'b0000_0000_0000_0000
                                      1: means CW maximum is 16'b0000_0000_0000_0001
                                      2: means CW maximum is 16'b0000_0000_0000_0011
                                      ...
                                      n: means CW maximum is (2^n - 1)
                                      ...
                                     16: means CW maximum is 16'b1111_1111_1111_1111
                                     17~31: reserved
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC00[28..24]         - (RO) The current contention window in unit of slot for AC00. The value is always (2^n - 1).
                                     0: means current CW is 16'b0000_0000_0000_0000
                                      1: means current CW is 16'b0000_0000_0000_0001
                                      2: means current CW is 16'b0000_0000_0000_0011
                                      ...
                                      n: means current CW is (2^n - 1)
                                      ...
                                     16: means current CW is 16'b1111_1111_1111_1111
                                     17~31: reserved
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC00_CURR_CW_AC00_ADDR               BN0_WF_ARB_TOP_WMMAC00_ADDR
#define BN0_WF_ARB_TOP_WMMAC00_CURR_CW_AC00_MASK               0x1F000000                // CURR_CW_AC00[28..24]
#define BN0_WF_ARB_TOP_WMMAC00_CURR_CW_AC00_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC00_CWMAX_AC00_ADDR                 BN0_WF_ARB_TOP_WMMAC00_ADDR
#define BN0_WF_ARB_TOP_WMMAC00_CWMAX_AC00_MASK                 0x001F0000                // CWMAX_AC00[20..16]
#define BN0_WF_ARB_TOP_WMMAC00_CWMAX_AC00_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC00_CWMIN_AC00_ADDR                 BN0_WF_ARB_TOP_WMMAC00_ADDR
#define BN0_WF_ARB_TOP_WMMAC00_CWMIN_AC00_MASK                 0x00001F00                // CWMIN_AC00[12..8]
#define BN0_WF_ARB_TOP_WMMAC00_CWMIN_AC00_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC00_AIFS_AC00_ADDR                  BN0_WF_ARB_TOP_WMMAC00_ADDR
#define BN0_WF_ARB_TOP_WMMAC00_AIFS_AC00_MASK                  0x0000000F                // AIFS_AC00[3..0]
#define BN0_WF_ARB_TOP_WMMAC00_AIFS_AC00_SHFT                  0

/* =====================================================================================

  ---WMMAC01 (0x820E3000 + 0x1A4)---

    AIFS_AC01[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC01[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC01[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC01[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC01_CURR_CW_AC01_ADDR               BN0_WF_ARB_TOP_WMMAC01_ADDR
#define BN0_WF_ARB_TOP_WMMAC01_CURR_CW_AC01_MASK               0x1F000000                // CURR_CW_AC01[28..24]
#define BN0_WF_ARB_TOP_WMMAC01_CURR_CW_AC01_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC01_CWMAX_AC01_ADDR                 BN0_WF_ARB_TOP_WMMAC01_ADDR
#define BN0_WF_ARB_TOP_WMMAC01_CWMAX_AC01_MASK                 0x001F0000                // CWMAX_AC01[20..16]
#define BN0_WF_ARB_TOP_WMMAC01_CWMAX_AC01_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC01_CWMIN_AC01_ADDR                 BN0_WF_ARB_TOP_WMMAC01_ADDR
#define BN0_WF_ARB_TOP_WMMAC01_CWMIN_AC01_MASK                 0x00001F00                // CWMIN_AC01[12..8]
#define BN0_WF_ARB_TOP_WMMAC01_CWMIN_AC01_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC01_AIFS_AC01_ADDR                  BN0_WF_ARB_TOP_WMMAC01_ADDR
#define BN0_WF_ARB_TOP_WMMAC01_AIFS_AC01_MASK                  0x0000000F                // AIFS_AC01[3..0]
#define BN0_WF_ARB_TOP_WMMAC01_AIFS_AC01_SHFT                  0

/* =====================================================================================

  ---WMMAC02 (0x820E3000 + 0x1A8)---

    AIFS_AC02[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC02[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC02[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC02[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC02_CURR_CW_AC02_ADDR               BN0_WF_ARB_TOP_WMMAC02_ADDR
#define BN0_WF_ARB_TOP_WMMAC02_CURR_CW_AC02_MASK               0x1F000000                // CURR_CW_AC02[28..24]
#define BN0_WF_ARB_TOP_WMMAC02_CURR_CW_AC02_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC02_CWMAX_AC02_ADDR                 BN0_WF_ARB_TOP_WMMAC02_ADDR
#define BN0_WF_ARB_TOP_WMMAC02_CWMAX_AC02_MASK                 0x001F0000                // CWMAX_AC02[20..16]
#define BN0_WF_ARB_TOP_WMMAC02_CWMAX_AC02_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC02_CWMIN_AC02_ADDR                 BN0_WF_ARB_TOP_WMMAC02_ADDR
#define BN0_WF_ARB_TOP_WMMAC02_CWMIN_AC02_MASK                 0x00001F00                // CWMIN_AC02[12..8]
#define BN0_WF_ARB_TOP_WMMAC02_CWMIN_AC02_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC02_AIFS_AC02_ADDR                  BN0_WF_ARB_TOP_WMMAC02_ADDR
#define BN0_WF_ARB_TOP_WMMAC02_AIFS_AC02_MASK                  0x0000000F                // AIFS_AC02[3..0]
#define BN0_WF_ARB_TOP_WMMAC02_AIFS_AC02_SHFT                  0

/* =====================================================================================

  ---WMMAC03 (0x820E3000 + 0x1AC)---

    AIFS_AC03[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC03[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC03[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC03[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC03_CURR_CW_AC03_ADDR               BN0_WF_ARB_TOP_WMMAC03_ADDR
#define BN0_WF_ARB_TOP_WMMAC03_CURR_CW_AC03_MASK               0x1F000000                // CURR_CW_AC03[28..24]
#define BN0_WF_ARB_TOP_WMMAC03_CURR_CW_AC03_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC03_CWMAX_AC03_ADDR                 BN0_WF_ARB_TOP_WMMAC03_ADDR
#define BN0_WF_ARB_TOP_WMMAC03_CWMAX_AC03_MASK                 0x001F0000                // CWMAX_AC03[20..16]
#define BN0_WF_ARB_TOP_WMMAC03_CWMAX_AC03_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC03_CWMIN_AC03_ADDR                 BN0_WF_ARB_TOP_WMMAC03_ADDR
#define BN0_WF_ARB_TOP_WMMAC03_CWMIN_AC03_MASK                 0x00001F00                // CWMIN_AC03[12..8]
#define BN0_WF_ARB_TOP_WMMAC03_CWMIN_AC03_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC03_AIFS_AC03_ADDR                  BN0_WF_ARB_TOP_WMMAC03_ADDR
#define BN0_WF_ARB_TOP_WMMAC03_AIFS_AC03_MASK                  0x0000000F                // AIFS_AC03[3..0]
#define BN0_WF_ARB_TOP_WMMAC03_AIFS_AC03_SHFT                  0

/* =====================================================================================

  ---WMMAC10 (0x820E3000 + 0x1B0)---

    AIFS_AC10[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC10[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC10[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC10[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC10_CURR_CW_AC10_ADDR               BN0_WF_ARB_TOP_WMMAC10_ADDR
#define BN0_WF_ARB_TOP_WMMAC10_CURR_CW_AC10_MASK               0x1F000000                // CURR_CW_AC10[28..24]
#define BN0_WF_ARB_TOP_WMMAC10_CURR_CW_AC10_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC10_CWMAX_AC10_ADDR                 BN0_WF_ARB_TOP_WMMAC10_ADDR
#define BN0_WF_ARB_TOP_WMMAC10_CWMAX_AC10_MASK                 0x001F0000                // CWMAX_AC10[20..16]
#define BN0_WF_ARB_TOP_WMMAC10_CWMAX_AC10_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC10_CWMIN_AC10_ADDR                 BN0_WF_ARB_TOP_WMMAC10_ADDR
#define BN0_WF_ARB_TOP_WMMAC10_CWMIN_AC10_MASK                 0x00001F00                // CWMIN_AC10[12..8]
#define BN0_WF_ARB_TOP_WMMAC10_CWMIN_AC10_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC10_AIFS_AC10_ADDR                  BN0_WF_ARB_TOP_WMMAC10_ADDR
#define BN0_WF_ARB_TOP_WMMAC10_AIFS_AC10_MASK                  0x0000000F                // AIFS_AC10[3..0]
#define BN0_WF_ARB_TOP_WMMAC10_AIFS_AC10_SHFT                  0

/* =====================================================================================

  ---WMMAC11 (0x820E3000 + 0x1B4)---

    AIFS_AC11[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC11[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC11[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC11[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC11_CURR_CW_AC11_ADDR               BN0_WF_ARB_TOP_WMMAC11_ADDR
#define BN0_WF_ARB_TOP_WMMAC11_CURR_CW_AC11_MASK               0x1F000000                // CURR_CW_AC11[28..24]
#define BN0_WF_ARB_TOP_WMMAC11_CURR_CW_AC11_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC11_CWMAX_AC11_ADDR                 BN0_WF_ARB_TOP_WMMAC11_ADDR
#define BN0_WF_ARB_TOP_WMMAC11_CWMAX_AC11_MASK                 0x001F0000                // CWMAX_AC11[20..16]
#define BN0_WF_ARB_TOP_WMMAC11_CWMAX_AC11_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC11_CWMIN_AC11_ADDR                 BN0_WF_ARB_TOP_WMMAC11_ADDR
#define BN0_WF_ARB_TOP_WMMAC11_CWMIN_AC11_MASK                 0x00001F00                // CWMIN_AC11[12..8]
#define BN0_WF_ARB_TOP_WMMAC11_CWMIN_AC11_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC11_AIFS_AC11_ADDR                  BN0_WF_ARB_TOP_WMMAC11_ADDR
#define BN0_WF_ARB_TOP_WMMAC11_AIFS_AC11_MASK                  0x0000000F                // AIFS_AC11[3..0]
#define BN0_WF_ARB_TOP_WMMAC11_AIFS_AC11_SHFT                  0

/* =====================================================================================

  ---WMMAC12 (0x820E3000 + 0x1B8)---

    AIFS_AC12[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC12[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC12[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC12[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC12_CURR_CW_AC12_ADDR               BN0_WF_ARB_TOP_WMMAC12_ADDR
#define BN0_WF_ARB_TOP_WMMAC12_CURR_CW_AC12_MASK               0x1F000000                // CURR_CW_AC12[28..24]
#define BN0_WF_ARB_TOP_WMMAC12_CURR_CW_AC12_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC12_CWMAX_AC12_ADDR                 BN0_WF_ARB_TOP_WMMAC12_ADDR
#define BN0_WF_ARB_TOP_WMMAC12_CWMAX_AC12_MASK                 0x001F0000                // CWMAX_AC12[20..16]
#define BN0_WF_ARB_TOP_WMMAC12_CWMAX_AC12_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC12_CWMIN_AC12_ADDR                 BN0_WF_ARB_TOP_WMMAC12_ADDR
#define BN0_WF_ARB_TOP_WMMAC12_CWMIN_AC12_MASK                 0x00001F00                // CWMIN_AC12[12..8]
#define BN0_WF_ARB_TOP_WMMAC12_CWMIN_AC12_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC12_AIFS_AC12_ADDR                  BN0_WF_ARB_TOP_WMMAC12_ADDR
#define BN0_WF_ARB_TOP_WMMAC12_AIFS_AC12_MASK                  0x0000000F                // AIFS_AC12[3..0]
#define BN0_WF_ARB_TOP_WMMAC12_AIFS_AC12_SHFT                  0

/* =====================================================================================

  ---WMMAC13 (0x820E3000 + 0x1BC)---

    AIFS_AC13[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC13[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC13[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC13[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC13_CURR_CW_AC13_ADDR               BN0_WF_ARB_TOP_WMMAC13_ADDR
#define BN0_WF_ARB_TOP_WMMAC13_CURR_CW_AC13_MASK               0x1F000000                // CURR_CW_AC13[28..24]
#define BN0_WF_ARB_TOP_WMMAC13_CURR_CW_AC13_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC13_CWMAX_AC13_ADDR                 BN0_WF_ARB_TOP_WMMAC13_ADDR
#define BN0_WF_ARB_TOP_WMMAC13_CWMAX_AC13_MASK                 0x001F0000                // CWMAX_AC13[20..16]
#define BN0_WF_ARB_TOP_WMMAC13_CWMAX_AC13_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC13_CWMIN_AC13_ADDR                 BN0_WF_ARB_TOP_WMMAC13_ADDR
#define BN0_WF_ARB_TOP_WMMAC13_CWMIN_AC13_MASK                 0x00001F00                // CWMIN_AC13[12..8]
#define BN0_WF_ARB_TOP_WMMAC13_CWMIN_AC13_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC13_AIFS_AC13_ADDR                  BN0_WF_ARB_TOP_WMMAC13_ADDR
#define BN0_WF_ARB_TOP_WMMAC13_AIFS_AC13_MASK                  0x0000000F                // AIFS_AC13[3..0]
#define BN0_WF_ARB_TOP_WMMAC13_AIFS_AC13_SHFT                  0

/* =====================================================================================

  ---WMMAC20 (0x820E3000 + 0x1C0)---

    AIFS_AC20[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC20[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC20[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC20[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC20_CURR_CW_AC20_ADDR               BN0_WF_ARB_TOP_WMMAC20_ADDR
#define BN0_WF_ARB_TOP_WMMAC20_CURR_CW_AC20_MASK               0x1F000000                // CURR_CW_AC20[28..24]
#define BN0_WF_ARB_TOP_WMMAC20_CURR_CW_AC20_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC20_CWMAX_AC20_ADDR                 BN0_WF_ARB_TOP_WMMAC20_ADDR
#define BN0_WF_ARB_TOP_WMMAC20_CWMAX_AC20_MASK                 0x001F0000                // CWMAX_AC20[20..16]
#define BN0_WF_ARB_TOP_WMMAC20_CWMAX_AC20_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC20_CWMIN_AC20_ADDR                 BN0_WF_ARB_TOP_WMMAC20_ADDR
#define BN0_WF_ARB_TOP_WMMAC20_CWMIN_AC20_MASK                 0x00001F00                // CWMIN_AC20[12..8]
#define BN0_WF_ARB_TOP_WMMAC20_CWMIN_AC20_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC20_AIFS_AC20_ADDR                  BN0_WF_ARB_TOP_WMMAC20_ADDR
#define BN0_WF_ARB_TOP_WMMAC20_AIFS_AC20_MASK                  0x0000000F                // AIFS_AC20[3..0]
#define BN0_WF_ARB_TOP_WMMAC20_AIFS_AC20_SHFT                  0

/* =====================================================================================

  ---WMMAC21 (0x820E3000 + 0x1C4)---

    AIFS_AC21[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC21[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC21[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC21[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC21_CURR_CW_AC21_ADDR               BN0_WF_ARB_TOP_WMMAC21_ADDR
#define BN0_WF_ARB_TOP_WMMAC21_CURR_CW_AC21_MASK               0x1F000000                // CURR_CW_AC21[28..24]
#define BN0_WF_ARB_TOP_WMMAC21_CURR_CW_AC21_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC21_CWMAX_AC21_ADDR                 BN0_WF_ARB_TOP_WMMAC21_ADDR
#define BN0_WF_ARB_TOP_WMMAC21_CWMAX_AC21_MASK                 0x001F0000                // CWMAX_AC21[20..16]
#define BN0_WF_ARB_TOP_WMMAC21_CWMAX_AC21_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC21_CWMIN_AC21_ADDR                 BN0_WF_ARB_TOP_WMMAC21_ADDR
#define BN0_WF_ARB_TOP_WMMAC21_CWMIN_AC21_MASK                 0x00001F00                // CWMIN_AC21[12..8]
#define BN0_WF_ARB_TOP_WMMAC21_CWMIN_AC21_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC21_AIFS_AC21_ADDR                  BN0_WF_ARB_TOP_WMMAC21_ADDR
#define BN0_WF_ARB_TOP_WMMAC21_AIFS_AC21_MASK                  0x0000000F                // AIFS_AC21[3..0]
#define BN0_WF_ARB_TOP_WMMAC21_AIFS_AC21_SHFT                  0

/* =====================================================================================

  ---WMMAC22 (0x820E3000 + 0x1C8)---

    AIFS_AC22[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC22[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC22[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC22[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC22_CURR_CW_AC22_ADDR               BN0_WF_ARB_TOP_WMMAC22_ADDR
#define BN0_WF_ARB_TOP_WMMAC22_CURR_CW_AC22_MASK               0x1F000000                // CURR_CW_AC22[28..24]
#define BN0_WF_ARB_TOP_WMMAC22_CURR_CW_AC22_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC22_CWMAX_AC22_ADDR                 BN0_WF_ARB_TOP_WMMAC22_ADDR
#define BN0_WF_ARB_TOP_WMMAC22_CWMAX_AC22_MASK                 0x001F0000                // CWMAX_AC22[20..16]
#define BN0_WF_ARB_TOP_WMMAC22_CWMAX_AC22_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC22_CWMIN_AC22_ADDR                 BN0_WF_ARB_TOP_WMMAC22_ADDR
#define BN0_WF_ARB_TOP_WMMAC22_CWMIN_AC22_MASK                 0x00001F00                // CWMIN_AC22[12..8]
#define BN0_WF_ARB_TOP_WMMAC22_CWMIN_AC22_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC22_AIFS_AC22_ADDR                  BN0_WF_ARB_TOP_WMMAC22_ADDR
#define BN0_WF_ARB_TOP_WMMAC22_AIFS_AC22_MASK                  0x0000000F                // AIFS_AC22[3..0]
#define BN0_WF_ARB_TOP_WMMAC22_AIFS_AC22_SHFT                  0

/* =====================================================================================

  ---WMMAC23 (0x820E3000 + 0x1CC)---

    AIFS_AC23[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC23[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC23[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC23[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC23_CURR_CW_AC23_ADDR               BN0_WF_ARB_TOP_WMMAC23_ADDR
#define BN0_WF_ARB_TOP_WMMAC23_CURR_CW_AC23_MASK               0x1F000000                // CURR_CW_AC23[28..24]
#define BN0_WF_ARB_TOP_WMMAC23_CURR_CW_AC23_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC23_CWMAX_AC23_ADDR                 BN0_WF_ARB_TOP_WMMAC23_ADDR
#define BN0_WF_ARB_TOP_WMMAC23_CWMAX_AC23_MASK                 0x001F0000                // CWMAX_AC23[20..16]
#define BN0_WF_ARB_TOP_WMMAC23_CWMAX_AC23_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC23_CWMIN_AC23_ADDR                 BN0_WF_ARB_TOP_WMMAC23_ADDR
#define BN0_WF_ARB_TOP_WMMAC23_CWMIN_AC23_MASK                 0x00001F00                // CWMIN_AC23[12..8]
#define BN0_WF_ARB_TOP_WMMAC23_CWMIN_AC23_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC23_AIFS_AC23_ADDR                  BN0_WF_ARB_TOP_WMMAC23_ADDR
#define BN0_WF_ARB_TOP_WMMAC23_AIFS_AC23_MASK                  0x0000000F                // AIFS_AC23[3..0]
#define BN0_WF_ARB_TOP_WMMAC23_AIFS_AC23_SHFT                  0

/* =====================================================================================

  ---WMMAC30 (0x820E3000 + 0x1D0)---

    AIFS_AC30[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC30[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC30[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC30[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC30_CURR_CW_AC30_ADDR               BN0_WF_ARB_TOP_WMMAC30_ADDR
#define BN0_WF_ARB_TOP_WMMAC30_CURR_CW_AC30_MASK               0x1F000000                // CURR_CW_AC30[28..24]
#define BN0_WF_ARB_TOP_WMMAC30_CURR_CW_AC30_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC30_CWMAX_AC30_ADDR                 BN0_WF_ARB_TOP_WMMAC30_ADDR
#define BN0_WF_ARB_TOP_WMMAC30_CWMAX_AC30_MASK                 0x001F0000                // CWMAX_AC30[20..16]
#define BN0_WF_ARB_TOP_WMMAC30_CWMAX_AC30_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC30_CWMIN_AC30_ADDR                 BN0_WF_ARB_TOP_WMMAC30_ADDR
#define BN0_WF_ARB_TOP_WMMAC30_CWMIN_AC30_MASK                 0x00001F00                // CWMIN_AC30[12..8]
#define BN0_WF_ARB_TOP_WMMAC30_CWMIN_AC30_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC30_AIFS_AC30_ADDR                  BN0_WF_ARB_TOP_WMMAC30_ADDR
#define BN0_WF_ARB_TOP_WMMAC30_AIFS_AC30_MASK                  0x0000000F                // AIFS_AC30[3..0]
#define BN0_WF_ARB_TOP_WMMAC30_AIFS_AC30_SHFT                  0

/* =====================================================================================

  ---WMMAC31 (0x820E3000 + 0x1D4)---

    AIFS_AC31[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC31[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC31[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC31[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC31_CURR_CW_AC31_ADDR               BN0_WF_ARB_TOP_WMMAC31_ADDR
#define BN0_WF_ARB_TOP_WMMAC31_CURR_CW_AC31_MASK               0x1F000000                // CURR_CW_AC31[28..24]
#define BN0_WF_ARB_TOP_WMMAC31_CURR_CW_AC31_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC31_CWMAX_AC31_ADDR                 BN0_WF_ARB_TOP_WMMAC31_ADDR
#define BN0_WF_ARB_TOP_WMMAC31_CWMAX_AC31_MASK                 0x001F0000                // CWMAX_AC31[20..16]
#define BN0_WF_ARB_TOP_WMMAC31_CWMAX_AC31_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC31_CWMIN_AC31_ADDR                 BN0_WF_ARB_TOP_WMMAC31_ADDR
#define BN0_WF_ARB_TOP_WMMAC31_CWMIN_AC31_MASK                 0x00001F00                // CWMIN_AC31[12..8]
#define BN0_WF_ARB_TOP_WMMAC31_CWMIN_AC31_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC31_AIFS_AC31_ADDR                  BN0_WF_ARB_TOP_WMMAC31_ADDR
#define BN0_WF_ARB_TOP_WMMAC31_AIFS_AC31_MASK                  0x0000000F                // AIFS_AC31[3..0]
#define BN0_WF_ARB_TOP_WMMAC31_AIFS_AC31_SHFT                  0

/* =====================================================================================

  ---WMMAC32 (0x820E3000 + 0x1D8)---

    AIFS_AC32[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC32[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC32[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC32[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC32_CURR_CW_AC32_ADDR               BN0_WF_ARB_TOP_WMMAC32_ADDR
#define BN0_WF_ARB_TOP_WMMAC32_CURR_CW_AC32_MASK               0x1F000000                // CURR_CW_AC32[28..24]
#define BN0_WF_ARB_TOP_WMMAC32_CURR_CW_AC32_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC32_CWMAX_AC32_ADDR                 BN0_WF_ARB_TOP_WMMAC32_ADDR
#define BN0_WF_ARB_TOP_WMMAC32_CWMAX_AC32_MASK                 0x001F0000                // CWMAX_AC32[20..16]
#define BN0_WF_ARB_TOP_WMMAC32_CWMAX_AC32_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC32_CWMIN_AC32_ADDR                 BN0_WF_ARB_TOP_WMMAC32_ADDR
#define BN0_WF_ARB_TOP_WMMAC32_CWMIN_AC32_MASK                 0x00001F00                // CWMIN_AC32[12..8]
#define BN0_WF_ARB_TOP_WMMAC32_CWMIN_AC32_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC32_AIFS_AC32_ADDR                  BN0_WF_ARB_TOP_WMMAC32_ADDR
#define BN0_WF_ARB_TOP_WMMAC32_AIFS_AC32_MASK                  0x0000000F                // AIFS_AC32[3..0]
#define BN0_WF_ARB_TOP_WMMAC32_AIFS_AC32_SHFT                  0

/* =====================================================================================

  ---WMMAC33 (0x820E3000 + 0x1DC)---

    AIFS_AC33[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[7..4]              - (RO) Reserved bits
    CWMIN_AC33[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_AC33[20..16]           - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_AC33[28..24]         - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMAC33_CURR_CW_AC33_ADDR               BN0_WF_ARB_TOP_WMMAC33_ADDR
#define BN0_WF_ARB_TOP_WMMAC33_CURR_CW_AC33_MASK               0x1F000000                // CURR_CW_AC33[28..24]
#define BN0_WF_ARB_TOP_WMMAC33_CURR_CW_AC33_SHFT               24
#define BN0_WF_ARB_TOP_WMMAC33_CWMAX_AC33_ADDR                 BN0_WF_ARB_TOP_WMMAC33_ADDR
#define BN0_WF_ARB_TOP_WMMAC33_CWMAX_AC33_MASK                 0x001F0000                // CWMAX_AC33[20..16]
#define BN0_WF_ARB_TOP_WMMAC33_CWMAX_AC33_SHFT                 16
#define BN0_WF_ARB_TOP_WMMAC33_CWMIN_AC33_ADDR                 BN0_WF_ARB_TOP_WMMAC33_ADDR
#define BN0_WF_ARB_TOP_WMMAC33_CWMIN_AC33_MASK                 0x00001F00                // CWMIN_AC33[12..8]
#define BN0_WF_ARB_TOP_WMMAC33_CWMIN_AC33_SHFT                 8
#define BN0_WF_ARB_TOP_WMMAC33_AIFS_AC33_ADDR                  BN0_WF_ARB_TOP_WMMAC33_ADDR
#define BN0_WF_ARB_TOP_WMMAC33_AIFS_AC33_MASK                  0x0000000F                // AIFS_AC33[3..0]
#define BN0_WF_ARB_TOP_WMMAC33_AIFS_AC33_SHFT                  0

/* =====================================================================================

  ---WMMALTX0 (0x820E3000 + 0x1E0)---

    AIFS_ALTX0[3..0]             - (RW) The same as AIFS_AC00.
    RESERVED4[6..4]              - (RO) Reserved bits
    SLOT_IDLE_ALTX0_SEL[7]       - (RW)  xxx 
    CWMIN_ALTX0[12..8]           - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_ALTX0[20..16]          - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_ALTX0[28..24]        - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMALTX0_CURR_CW_ALTX0_ADDR             BN0_WF_ARB_TOP_WMMALTX0_ADDR
#define BN0_WF_ARB_TOP_WMMALTX0_CURR_CW_ALTX0_MASK             0x1F000000                // CURR_CW_ALTX0[28..24]
#define BN0_WF_ARB_TOP_WMMALTX0_CURR_CW_ALTX0_SHFT             24
#define BN0_WF_ARB_TOP_WMMALTX0_CWMAX_ALTX0_ADDR               BN0_WF_ARB_TOP_WMMALTX0_ADDR
#define BN0_WF_ARB_TOP_WMMALTX0_CWMAX_ALTX0_MASK               0x001F0000                // CWMAX_ALTX0[20..16]
#define BN0_WF_ARB_TOP_WMMALTX0_CWMAX_ALTX0_SHFT               16
#define BN0_WF_ARB_TOP_WMMALTX0_CWMIN_ALTX0_ADDR               BN0_WF_ARB_TOP_WMMALTX0_ADDR
#define BN0_WF_ARB_TOP_WMMALTX0_CWMIN_ALTX0_MASK               0x00001F00                // CWMIN_ALTX0[12..8]
#define BN0_WF_ARB_TOP_WMMALTX0_CWMIN_ALTX0_SHFT               8
#define BN0_WF_ARB_TOP_WMMALTX0_SLOT_IDLE_ALTX0_SEL_ADDR       BN0_WF_ARB_TOP_WMMALTX0_ADDR
#define BN0_WF_ARB_TOP_WMMALTX0_SLOT_IDLE_ALTX0_SEL_MASK       0x00000080                // SLOT_IDLE_ALTX0_SEL[7]
#define BN0_WF_ARB_TOP_WMMALTX0_SLOT_IDLE_ALTX0_SEL_SHFT       7
#define BN0_WF_ARB_TOP_WMMALTX0_AIFS_ALTX0_ADDR                BN0_WF_ARB_TOP_WMMALTX0_ADDR
#define BN0_WF_ARB_TOP_WMMALTX0_AIFS_ALTX0_MASK                0x0000000F                // AIFS_ALTX0[3..0]
#define BN0_WF_ARB_TOP_WMMALTX0_AIFS_ALTX0_SHFT                0

/* =====================================================================================

  ---WMMBMC0 (0x820E3000 + 0x1E4)---

    AIFS_BMC0[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[6..4]              - (RO) Reserved bits
    SLOT_IDLE_BMC0_SEL[7]        - (RW)  xxx 
    CWMIN_BMC0[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMBMC0_CWMIN_BMC0_ADDR                 BN0_WF_ARB_TOP_WMMBMC0_ADDR
#define BN0_WF_ARB_TOP_WMMBMC0_CWMIN_BMC0_MASK                 0x00001F00                // CWMIN_BMC0[12..8]
#define BN0_WF_ARB_TOP_WMMBMC0_CWMIN_BMC0_SHFT                 8
#define BN0_WF_ARB_TOP_WMMBMC0_SLOT_IDLE_BMC0_SEL_ADDR         BN0_WF_ARB_TOP_WMMBMC0_ADDR
#define BN0_WF_ARB_TOP_WMMBMC0_SLOT_IDLE_BMC0_SEL_MASK         0x00000080                // SLOT_IDLE_BMC0_SEL[7]
#define BN0_WF_ARB_TOP_WMMBMC0_SLOT_IDLE_BMC0_SEL_SHFT         7
#define BN0_WF_ARB_TOP_WMMBMC0_AIFS_BMC0_ADDR                  BN0_WF_ARB_TOP_WMMBMC0_ADDR
#define BN0_WF_ARB_TOP_WMMBMC0_AIFS_BMC0_MASK                  0x0000000F                // AIFS_BMC0[3..0]
#define BN0_WF_ARB_TOP_WMMBMC0_AIFS_BMC0_SHFT                  0

/* =====================================================================================

  ---WMMBCN0 (0x820E3000 + 0x1E8)---

    AIFS_BCN0[3..0]              - (RW) The same as AIFS_AC00.
    RESERVED4[6..4]              - (RO) Reserved bits
    SLOT_IDLE_BNC0_SEL[7]        - (RW)  xxx 
    CWMIN_BCN0[12..8]            - (RW) The same as CWMIN_AC00.
    RESERVED13[31..13]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMBCN0_CWMIN_BCN0_ADDR                 BN0_WF_ARB_TOP_WMMBCN0_ADDR
#define BN0_WF_ARB_TOP_WMMBCN0_CWMIN_BCN0_MASK                 0x00001F00                // CWMIN_BCN0[12..8]
#define BN0_WF_ARB_TOP_WMMBCN0_CWMIN_BCN0_SHFT                 8
#define BN0_WF_ARB_TOP_WMMBCN0_SLOT_IDLE_BNC0_SEL_ADDR         BN0_WF_ARB_TOP_WMMBCN0_ADDR
#define BN0_WF_ARB_TOP_WMMBCN0_SLOT_IDLE_BNC0_SEL_MASK         0x00000080                // SLOT_IDLE_BNC0_SEL[7]
#define BN0_WF_ARB_TOP_WMMBCN0_SLOT_IDLE_BNC0_SEL_SHFT         7
#define BN0_WF_ARB_TOP_WMMBCN0_AIFS_BCN0_ADDR                  BN0_WF_ARB_TOP_WMMBCN0_ADDR
#define BN0_WF_ARB_TOP_WMMBCN0_AIFS_BCN0_MASK                  0x0000000F                // AIFS_BCN0[3..0]
#define BN0_WF_ARB_TOP_WMMBCN0_AIFS_BCN0_SHFT                  0

/* =====================================================================================

  ---WMMTXCMDALTX0 (0x820E3000 + 0x1EC)---

    AIFS_TXCMD_ALTX0[3..0]       - (RW) The same as AIFS_AC00.
    RESERVED4[6..4]              - (RO) Reserved bits
    SLOT_IDLE_TXCMD_ALTX0_SEL[7] - (RW)  xxx 
    CWMIN_TXCMD_ALTX0[12..8]     - (RW) The same as CWMIN_AC00.
    RESERVED13[15..13]           - (RO) Reserved bits
    CWMAX_TXCMD_ALTX0[20..16]    - (RW) The same as CWMAX_AC00.
    RESERVED21[23..21]           - (RO) Reserved bits
    CURR_CW_TXCMD_ALTX0[28..24]  - (RO) The same as CURR_CW_AC00.
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_CURR_CW_TXCMD_ALTX0_ADDR  BN0_WF_ARB_TOP_WMMTXCMDALTX0_ADDR
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_CURR_CW_TXCMD_ALTX0_MASK  0x1F000000                // CURR_CW_TXCMD_ALTX0[28..24]
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_CURR_CW_TXCMD_ALTX0_SHFT  24
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_CWMAX_TXCMD_ALTX0_ADDR    BN0_WF_ARB_TOP_WMMTXCMDALTX0_ADDR
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_CWMAX_TXCMD_ALTX0_MASK    0x001F0000                // CWMAX_TXCMD_ALTX0[20..16]
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_CWMAX_TXCMD_ALTX0_SHFT    16
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_CWMIN_TXCMD_ALTX0_ADDR    BN0_WF_ARB_TOP_WMMTXCMDALTX0_ADDR
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_CWMIN_TXCMD_ALTX0_MASK    0x00001F00                // CWMIN_TXCMD_ALTX0[12..8]
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_CWMIN_TXCMD_ALTX0_SHFT    8
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_SLOT_IDLE_TXCMD_ALTX0_SEL_ADDR BN0_WF_ARB_TOP_WMMTXCMDALTX0_ADDR
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_SLOT_IDLE_TXCMD_ALTX0_SEL_MASK 0x00000080                // SLOT_IDLE_TXCMD_ALTX0_SEL[7]
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_SLOT_IDLE_TXCMD_ALTX0_SEL_SHFT 7
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_AIFS_TXCMD_ALTX0_ADDR     BN0_WF_ARB_TOP_WMMTXCMDALTX0_ADDR
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_AIFS_TXCMD_ALTX0_MASK     0x0000000F                // AIFS_TXCMD_ALTX0[3..0]
#define BN0_WF_ARB_TOP_WMMTXCMDALTX0_AIFS_TXCMD_ALTX0_SHFT     0

/* =====================================================================================

  ---D0WPTAR (0x820E3000 + 0x200)---

    D0_PTA_ARB_EN[0]             - (RW) Enable PTA WiFi arbitration mode function
                                     (for DBDC channel 0)
    D0_PTA_BT_RW_EN[1]           - (RW) Enable PTA WiFi remaining window function from BT
                                     0: WIFISYS will ignore the window information from BT
                                     1: WIFISYS will honor remaining window setting from BT
                                     (for DBDC channel 0)
    D0_PTA_LTE_RW_EN[2]          - (RW) Enable PTA WiFi remaining window function from LTE
                                     0: WIFISYS will ignore the window information from LTE
                                     1: WIFISYS will honor remaining window setting from LTE
                                     (for DBDC channel 0)
    RESERVED3[3]                 - (RO) Reserved bits
    D0_PTA_BT_RW_EN_FDD[4]       - (RW) Enable PTA WiFi remaining window function from BT
                                     0: WIFISYS will ignore the window information from BT
                                     1: WIFISYS will honor remaining window setting from BT
                                     (for DBDC channel 0)
    RESERVED5[6..5]              - (RO) Reserved bits
    D0_PTA_MA2PHY_TX_SEL[7]      - (RW) The value will decide which is sent to AGG for controlling SN transfer to DMA/UMAC after TX success or failure.
                                     0: mac2phy_tx. 
                                     1: mac2phy_tx & pta_grant & wifi_tx_req
                                     During TX, if ARB_PTA does not get grant from PTA, the TX will be aborted or not be allowed. However, SN might still be transferred from AGG to DMA/UMAC depending on the setting of this bit.
    D0_PTA_ARB_MODE[8]           - (RW) PTA arbitration mode (Valid only when D0_PTA_ARB_EN=1)
                                     0: continue back off procedure when PTA assert pta_rxpwr_dis
                                     1: freeze back off procedure when PTA assert pta_rxpwr_dis
                                     (for DBDC channel 0)
    D0_PTA_TXOP_KEEP_EN[9]       - (RW) This field indicated TXOP keep or not when TXOP has established but PTA master don't give grant for PTA's Tx packet or its ACK.
                                     0: TXOP don't keep
                                     1: TXOP will keep
                                     (for DBDC channel 0)
    RESERVED10[11..10]           - (RO) Reserved bits
    D0_LEGACY_NULL[15..12]       - (RW) This field indicated Null type when use fast power saving method to protect BSS3/BSS2/BSS1/BSS0
                                      0: use QoS Null
                                      1: use legacy Null
                                     (for DBDC channel 0)
    D0_PTA_RW_MODE[20..16]       - (RW) PTA remaining window mode (Valid only when D0_PTA_RW_EN=1)
                                      pta_rw_mode[4] indicates using channel reservation or fast PS method protect.
                                     0: channel reservation
                                     1: fast PS method
                                      pta_rw_mode[3:0] indicates the enable for  BSSID3/2/1/0.
                                     0: disable
                                     1: enable
                                     When user select channel reservation, HW only issue a CTS2Self/CFEnd once with the smallest BSSID number which is enable. 
                                     While user select fast PS method, HW will try to issue several NULL packets with those BSSID are enabled.
                                     (for DBDC channel 0)
    RESERVED21[23..21]           - (RO) Reserved bits
    D0_SILENCE_WIN_PS_EN[27..24] - (RW) This field indicated the PS bit of all packets for BSS3/BSS2/BSS1/BSS0 into silence window.
                                     (only valid when the respective D0_PTA_RW_MODE bit is 1)
                                      0: PS bit of all packets is the same original define whether into silence window or not
                                      1: PS bit of all packets (include bufferable and non-bufferable packet, non-bufferable packet extra control by D0_SILENCE_WIN_NB_PS_EN) is always 1 when remaining window less than silence window; PS bit is the same original define when remaining window more than silence window.
                                     (for DBDC channel 0)
    D0_SILENCE_WIN_AIFS_EN[28]   - (RW) This field indicated AC queue enable enlarge AISF when remain window less than silence window.
                                      0: all AC queue's AIFS keep original setting when remain window less than silence window
                                      1: all AC queue's AIFS become D0_SILENCE_WIN_AIFS when remain window less than silence window
                                     (for DBDC channel 0)
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0WPTAR_D0_SILENCE_WIN_AIFS_EN_ADDR     BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_SILENCE_WIN_AIFS_EN_MASK     0x10000000                // D0_SILENCE_WIN_AIFS_EN[28]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_SILENCE_WIN_AIFS_EN_SHFT     28
#define BN0_WF_ARB_TOP_D0WPTAR_D0_SILENCE_WIN_PS_EN_ADDR       BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_SILENCE_WIN_PS_EN_MASK       0x0F000000                // D0_SILENCE_WIN_PS_EN[27..24]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_SILENCE_WIN_PS_EN_SHFT       24
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_RW_MODE_ADDR             BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_RW_MODE_MASK             0x001F0000                // D0_PTA_RW_MODE[20..16]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_RW_MODE_SHFT             16
#define BN0_WF_ARB_TOP_D0WPTAR_D0_LEGACY_NULL_ADDR             BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_LEGACY_NULL_MASK             0x0000F000                // D0_LEGACY_NULL[15..12]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_LEGACY_NULL_SHFT             12
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_TXOP_KEEP_EN_ADDR        BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_TXOP_KEEP_EN_MASK        0x00000200                // D0_PTA_TXOP_KEEP_EN[9]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_TXOP_KEEP_EN_SHFT        9
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_ARB_MODE_ADDR            BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_ARB_MODE_MASK            0x00000100                // D0_PTA_ARB_MODE[8]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_ARB_MODE_SHFT            8
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_MA2PHY_TX_SEL_ADDR       BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_MA2PHY_TX_SEL_MASK       0x00000080                // D0_PTA_MA2PHY_TX_SEL[7]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_MA2PHY_TX_SEL_SHFT       7
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_BT_RW_EN_FDD_ADDR        BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_BT_RW_EN_FDD_MASK        0x00000010                // D0_PTA_BT_RW_EN_FDD[4]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_BT_RW_EN_FDD_SHFT        4
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_LTE_RW_EN_ADDR           BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_LTE_RW_EN_MASK           0x00000004                // D0_PTA_LTE_RW_EN[2]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_LTE_RW_EN_SHFT           2
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_BT_RW_EN_ADDR            BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_BT_RW_EN_MASK            0x00000002                // D0_PTA_BT_RW_EN[1]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_BT_RW_EN_SHFT            1
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_ARB_EN_ADDR              BN0_WF_ARB_TOP_D0WPTAR_ADDR
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_ARB_EN_MASK              0x00000001                // D0_PTA_ARB_EN[0]
#define BN0_WF_ARB_TOP_D0WPTAR_D0_PTA_ARB_EN_SHFT              0

/* =====================================================================================

  ---D0PTR0 (0x820E3000 + 0x204)---

    D0_WLAN_AC0_TX_TAG[3..0]     - (RW) This field is used to indicate tag of AC00, AC10, AC20, AC30 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_AC1_TX_TAG[7..4]     - (RW) This field is used to indicate tag of AC01, AC11, AC21, AC31 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_AC2_TX_TAG[11..8]    - (RW) This field is used to indicate tag of AC02, AC12, AC22, AC32 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_AC3_TX_TAG[15..12]   - (RW) This field is used to indicate tag of AC03, AC13, AC23, AC33 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_ALTX0_TX_TAG[19..16] - (RW) This field is used to indicate tag of ALTX0 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_BMC_TX_TAG[23..20]   - (RW) This field is used to indicate tag of BMC0, BMC1 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_BCN_TX_TAG[27..24]   - (RW) This field is used to indicate tag of BCN0, BCN1 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_PSMP_TX_TAG[31..28]  - (RW) This field is used to indicate tag of  PSMP0, PSMP1 frame transmission to PTA
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_PSMP_TX_TAG_ADDR         BN0_WF_ARB_TOP_D0PTR0_ADDR
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_PSMP_TX_TAG_MASK         0xF0000000                // D0_WLAN_PSMP_TX_TAG[31..28]
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_PSMP_TX_TAG_SHFT         28
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_BCN_TX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR0_ADDR
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_BCN_TX_TAG_MASK          0x0F000000                // D0_WLAN_BCN_TX_TAG[27..24]
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_BCN_TX_TAG_SHFT          24
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_BMC_TX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR0_ADDR
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_BMC_TX_TAG_MASK          0x00F00000                // D0_WLAN_BMC_TX_TAG[23..20]
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_BMC_TX_TAG_SHFT          20
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_ALTX0_TX_TAG_ADDR        BN0_WF_ARB_TOP_D0PTR0_ADDR
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_ALTX0_TX_TAG_MASK        0x000F0000                // D0_WLAN_ALTX0_TX_TAG[19..16]
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_ALTX0_TX_TAG_SHFT        16
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC3_TX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR0_ADDR
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC3_TX_TAG_MASK          0x0000F000                // D0_WLAN_AC3_TX_TAG[15..12]
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC3_TX_TAG_SHFT          12
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC2_TX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR0_ADDR
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC2_TX_TAG_MASK          0x00000F00                // D0_WLAN_AC2_TX_TAG[11..8]
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC2_TX_TAG_SHFT          8
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC1_TX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR0_ADDR
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC1_TX_TAG_MASK          0x000000F0                // D0_WLAN_AC1_TX_TAG[7..4]
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC1_TX_TAG_SHFT          4
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC0_TX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR0_ADDR
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC0_TX_TAG_MASK          0x0000000F                // D0_WLAN_AC0_TX_TAG[3..0]
#define BN0_WF_ARB_TOP_D0PTR0_D0_WLAN_AC0_TX_TAG_SHFT          0

/* =====================================================================================

  ---D0PTR1 (0x820E3000 + 0x208)---

    D0_WLAN_AC0_RX_TAG[3..0]     - (RW) This field is used to indicate tag of RX ACK/BA sequence of AC00, AC10, AC20, AC30 frame to PTA
                                     (for DBDC channel 0)
    D0_WLAN_AC1_RX_TAG[7..4]     - (RW) This field is used to indicate tag of RX ACK/BA sequence of AC01, AC11, AC21, AC31 frame to PTA
                                     (for DBDC channel 0)
    D0_WLAN_AC2_RX_TAG[11..8]    - (RW) This field is used to indicate tag of RX ACK/BA sequence of AC02, AC12, AC22, AC32 frame to PTA
                                     (for DBDC channel 0)
    D0_WLAN_AC3_RX_TAG[15..12]   - (RW) This field is used to indicate tag of RX ACK/BA sequence of AC03, AC13, Ac23, AC33 frame to PTA
                                     (for DBDC channel 0)
    D0_WLAN_ALTX0_RX_TAG[19..16] - (RW) This field is used to indicate tag of RX ACK sequence of ALTX0 frame to PTA
                                     (for DBDC channel 0)
    RESERVED20[27..20]           - (RO) Reserved bits
    D0_WLAN_PSMP_RX_TAG[31..28]  - (RW) This field is used to indicate tag of RX ACK/BA sequence of PSMP0, PSMP1 frame to PTA
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_PSMP_RX_TAG_ADDR         BN0_WF_ARB_TOP_D0PTR1_ADDR
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_PSMP_RX_TAG_MASK         0xF0000000                // D0_WLAN_PSMP_RX_TAG[31..28]
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_PSMP_RX_TAG_SHFT         28
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_ALTX0_RX_TAG_ADDR        BN0_WF_ARB_TOP_D0PTR1_ADDR
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_ALTX0_RX_TAG_MASK        0x000F0000                // D0_WLAN_ALTX0_RX_TAG[19..16]
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_ALTX0_RX_TAG_SHFT        16
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC3_RX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR1_ADDR
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC3_RX_TAG_MASK          0x0000F000                // D0_WLAN_AC3_RX_TAG[15..12]
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC3_RX_TAG_SHFT          12
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC2_RX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR1_ADDR
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC2_RX_TAG_MASK          0x00000F00                // D0_WLAN_AC2_RX_TAG[11..8]
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC2_RX_TAG_SHFT          8
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC1_RX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR1_ADDR
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC1_RX_TAG_MASK          0x000000F0                // D0_WLAN_AC1_RX_TAG[7..4]
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC1_RX_TAG_SHFT          4
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC0_RX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR1_ADDR
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC0_RX_TAG_MASK          0x0000000F                // D0_WLAN_AC0_RX_TAG[3..0]
#define BN0_WF_ARB_TOP_D0PTR1_D0_WLAN_AC0_RX_TAG_SHFT          0

/* =====================================================================================

  ---D0PTR2 (0x820E3000 + 0x20C)---

    D0_WLAN_PTA_RX_TAG[3..0]     - (RW) This field is used to indicate tag to PTA when RX frame that responding the frames transmitted by WiFi PTA (for example, receive ack of QoS-NULL frame).
                                     (for DBDC channel 0)
    D0_WLAN_PTA_TX_TAG[7..4]     - (RW) This field is used to indicate the tag of frames (transmitted by WiFi PTA, for example, CTS2Self, CF-END, QoS-NULL) to PTA
                                     (for DBDC channel 0)
    D0_WLAN_SP_RX_TAG[11..8]     - (RW) This field is used to indicate tag to PTA when RX frames in known SP (service period) (for example, beacon frame or RX BCM frame during  BMC service period or DTT period. )
                                     (for DBDC channel 0)
    D0_WLAN_BFEE_TX_TAG[15..12]  - (RW) This field is used to indicate tag to PTA when TX a beamforming response packet as be a beamformee.
                                     (for DBDC channel 0)
    D0_WLAN_TX_RSP_TAG[19..16]   - (RW) This field is used to indicate the tag of TX ACK/BA to PTA
                                     (for DBDC channel 0)
    D0_WLAN_RX_NSW_TAG[23..20]   - (RW) This field is used to indicate the tag of RX_PE/CCA/CCA_CS/mdrdy asserted to PTA
                                     (for DBDC channel 0)
    D0_WLAN_RX_NSW_MODE[25..24]  - (RW) This field is used to define when to assert NSW (Not Sure When) Rx Request. This field is applicable for "RX Request - Not sure when" scenario.
                                     0x0: Assert rx request when MDRDY is asserted
                                     0x1: Assert rx request when CCA_CS is asserted
                                     0x2: Assert rx request when CCA is asserted
                                     0x3: Assert rx request when RX_PE is asserted
                                     (for DBDC channel 0)
    D0_WLAN_SP_RX_BD_EN[26]      - (RW) SW backdoor SP (service period). HW always assert rx request with D0_WLAN_SP_RX_TAG
                                     (for DBDC channel 0)
    D0_WLAN_SP_HPRI_EN[27]       - (RW) WLAN service period high priority (Only valid when MCUSYS in sleep mode)
                                     This field can enable high priority for all service period. I.E. HW will assert wifi_hpri in service period if D0_WLAN_SP_HPRI_EN. When MCUSYS in sleep mode, the PTA's ext_grant is directly express as: ext_grant = ~wifi_hpri. (bypass all DFF because MCUSYS's clock maybe disable) In fact, D0_WLAN_SP_HPRI_EN can guarantee WiFi no interference from external device (WiMAX)
                                     (for DBDC channel 0)
    TAG_GUARD_TIME[31..28]       - (RW) This field is for HW implementation-specific setting for asynchronous circuit.
                                     SW don't need to care what it means. DE will take care this setting.
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTR2_TAG_GUARD_TIME_ADDR              BN0_WF_ARB_TOP_D0PTR2_ADDR
#define BN0_WF_ARB_TOP_D0PTR2_TAG_GUARD_TIME_MASK              0xF0000000                // TAG_GUARD_TIME[31..28]
#define BN0_WF_ARB_TOP_D0PTR2_TAG_GUARD_TIME_SHFT              28
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_SP_HPRI_EN_ADDR          BN0_WF_ARB_TOP_D0PTR2_ADDR
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_SP_HPRI_EN_MASK          0x08000000                // D0_WLAN_SP_HPRI_EN[27]
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_SP_HPRI_EN_SHFT          27
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_SP_RX_BD_EN_ADDR         BN0_WF_ARB_TOP_D0PTR2_ADDR
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_SP_RX_BD_EN_MASK         0x04000000                // D0_WLAN_SP_RX_BD_EN[26]
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_SP_RX_BD_EN_SHFT         26
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_RX_NSW_MODE_ADDR         BN0_WF_ARB_TOP_D0PTR2_ADDR
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_RX_NSW_MODE_MASK         0x03000000                // D0_WLAN_RX_NSW_MODE[25..24]
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_RX_NSW_MODE_SHFT         24
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_RX_NSW_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR2_ADDR
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_RX_NSW_TAG_MASK          0x00F00000                // D0_WLAN_RX_NSW_TAG[23..20]
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_RX_NSW_TAG_SHFT          20
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_TX_RSP_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR2_ADDR
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_TX_RSP_TAG_MASK          0x000F0000                // D0_WLAN_TX_RSP_TAG[19..16]
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_TX_RSP_TAG_SHFT          16
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_BFEE_TX_TAG_ADDR         BN0_WF_ARB_TOP_D0PTR2_ADDR
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_BFEE_TX_TAG_MASK         0x0000F000                // D0_WLAN_BFEE_TX_TAG[15..12]
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_BFEE_TX_TAG_SHFT         12
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_SP_RX_TAG_ADDR           BN0_WF_ARB_TOP_D0PTR2_ADDR
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_SP_RX_TAG_MASK           0x00000F00                // D0_WLAN_SP_RX_TAG[11..8]
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_SP_RX_TAG_SHFT           8
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_PTA_TX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR2_ADDR
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_PTA_TX_TAG_MASK          0x000000F0                // D0_WLAN_PTA_TX_TAG[7..4]
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_PTA_TX_TAG_SHFT          4
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_PTA_RX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR2_ADDR
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_PTA_RX_TAG_MASK          0x0000000F                // D0_WLAN_PTA_RX_TAG[3..0]
#define BN0_WF_ARB_TOP_D0PTR2_D0_WLAN_PTA_RX_TAG_SHFT          0

/* =====================================================================================

  ---D0PTR3 (0x820E3000 + 0x210)---

    D0_WLAN_NAF_TX_TAG[3..0]     - (RW) This field is used to indicate tag of NAN action frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_NBCN_TX_TAG[7..4]    - (RW) This field is used to indicate tag of NAN beacon frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    RESERVED8[15..8]             - (RO) Reserved bits
    D0_WLAN_NAF_RX_TAG[19..16]   - (RW) This field is used to indicate tag of RX ACK/BA sequence of NAN action frame to PTA
                                     (for DBDC channel 0)
    RESERVED20[23..20]           - (RO) Reserved bits
    D0_WLAN_PTA_RX_TAG2[27..24]  - (RW) The meaning of this field is the similar as D0_WLAN_PTA_RX_TAG. But it is applied in the condition that urgent CTS or PSON period (first CTS or cascade CTS)
                                     The definition of urgent is those RWP transmitted when D0_CTS_REISSUE_EN=1 or D0_CTS_MAXREMWIN_EN=1 or D0_PSON_MAXREMWIN_EN = 1
                                     (for DBDC channel 0)
    D0_WLAN_PTA_TX_TAG2[31..28]  - (RW) The meaning of this field is the similar as D0_WLAN_PTA_TX_TAG. But it is applied in the condition that urgent CTS or PSON period (first CTS or cascade CTS)
                                     The definition of urgent is those RWP transmitted when D0_CTS_REISSUE_EN=1 or D0_CTS_MAXREMWIN_EN=1 or D0_PSON_MAXREMWIN_EN = 1
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_PTA_TX_TAG2_ADDR         BN0_WF_ARB_TOP_D0PTR3_ADDR
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_PTA_TX_TAG2_MASK         0xF0000000                // D0_WLAN_PTA_TX_TAG2[31..28]
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_PTA_TX_TAG2_SHFT         28
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_PTA_RX_TAG2_ADDR         BN0_WF_ARB_TOP_D0PTR3_ADDR
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_PTA_RX_TAG2_MASK         0x0F000000                // D0_WLAN_PTA_RX_TAG2[27..24]
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_PTA_RX_TAG2_SHFT         24
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_NAF_RX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR3_ADDR
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_NAF_RX_TAG_MASK          0x000F0000                // D0_WLAN_NAF_RX_TAG[19..16]
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_NAF_RX_TAG_SHFT          16
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_NBCN_TX_TAG_ADDR         BN0_WF_ARB_TOP_D0PTR3_ADDR
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_NBCN_TX_TAG_MASK         0x000000F0                // D0_WLAN_NBCN_TX_TAG[7..4]
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_NBCN_TX_TAG_SHFT         4
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_NAF_TX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR3_ADDR
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_NAF_TX_TAG_MASK          0x0000000F                // D0_WLAN_NAF_TX_TAG[3..0]
#define BN0_WF_ARB_TOP_D0PTR3_D0_WLAN_NAF_TX_TAG_SHFT          0

/* =====================================================================================

  ---D0PTR4 (0x820E3000 + 0x214)---

    D0_WLAN_TWTTSFTF0_TX_TAG[3..0] - (RW) This field is used to indicate tag of TWTTSFTF0 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_TWTUL0_TX_TAG[7..4]  - (RW) This field is used to indicate tag of TWTUL0 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_TWTDL0_TX_TAG[11..8] - (RW) This field is used to indicate tag of TWTDL0 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_ALTXCMD0_TX_TAG[15..12] - (RW) This field is used to indicate tag of ALTXCMD0 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    D0_WLAN_TF0_TX_TAG[19..16]   - (RW) This field is used to indicate tag of TF0 frame (including protection frame, for example RTS) transmission to PTA
                                     (for DBDC channel 0)
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TF0_TX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR4_ADDR
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TF0_TX_TAG_MASK          0x000F0000                // D0_WLAN_TF0_TX_TAG[19..16]
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TF0_TX_TAG_SHFT          16
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_ALTXCMD0_TX_TAG_ADDR     BN0_WF_ARB_TOP_D0PTR4_ADDR
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_ALTXCMD0_TX_TAG_MASK     0x0000F000                // D0_WLAN_ALTXCMD0_TX_TAG[15..12]
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_ALTXCMD0_TX_TAG_SHFT     12
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TWTDL0_TX_TAG_ADDR       BN0_WF_ARB_TOP_D0PTR4_ADDR
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TWTDL0_TX_TAG_MASK       0x00000F00                // D0_WLAN_TWTDL0_TX_TAG[11..8]
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TWTDL0_TX_TAG_SHFT       8
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TWTUL0_TX_TAG_ADDR       BN0_WF_ARB_TOP_D0PTR4_ADDR
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TWTUL0_TX_TAG_MASK       0x000000F0                // D0_WLAN_TWTUL0_TX_TAG[7..4]
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TWTUL0_TX_TAG_SHFT       4
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TWTTSFTF0_TX_TAG_ADDR    BN0_WF_ARB_TOP_D0PTR4_ADDR
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TWTTSFTF0_TX_TAG_MASK    0x0000000F                // D0_WLAN_TWTTSFTF0_TX_TAG[3..0]
#define BN0_WF_ARB_TOP_D0PTR4_D0_WLAN_TWTTSFTF0_TX_TAG_SHFT    0

/* =====================================================================================

  ---D0PTR5 (0x820E3000 + 0x218)---

    D0_WLAN_TWTTSFTF0_RX_TAG[3..0] - (RW) This field is used to indicate tag of RX ACK sequence of TWTTSFTF0 frame to PTA
                                     (for DBDC channel 0)
    D0_WLAN_TWTUL0_RX_TAG[7..4]  - (RW) This field is used to indicate tag of RX ACK sequence of TWTUL0 frame to PTA
                                     (for DBDC channel 0)
    D0_WLAN_TWTDL0_RX_TAG[11..8] - (RW) This field is used to indicate tag of RX ACK sequence of TWTDL0 frame to PTA
                                     (for DBDC channel 0)
    D0_WLAN_ALTXCMD0_RX_TAG[15..12] - (RW) This field is used to indicate tag of RX ACK sequence of ALTXCMD0 frame to PTA
                                     (for DBDC channel 0)
    D0_WLAN_TF0_RX_TAG[19..16]   - (RW) This field is used to indicate tag of RX ACK sequence of TF0 frame to PTA
                                     (for DBDC channel 0)
    RESERVED20[31..20]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TF0_RX_TAG_ADDR          BN0_WF_ARB_TOP_D0PTR5_ADDR
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TF0_RX_TAG_MASK          0x000F0000                // D0_WLAN_TF0_RX_TAG[19..16]
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TF0_RX_TAG_SHFT          16
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_ALTXCMD0_RX_TAG_ADDR     BN0_WF_ARB_TOP_D0PTR5_ADDR
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_ALTXCMD0_RX_TAG_MASK     0x0000F000                // D0_WLAN_ALTXCMD0_RX_TAG[15..12]
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_ALTXCMD0_RX_TAG_SHFT     12
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TWTDL0_RX_TAG_ADDR       BN0_WF_ARB_TOP_D0PTR5_ADDR
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TWTDL0_RX_TAG_MASK       0x00000F00                // D0_WLAN_TWTDL0_RX_TAG[11..8]
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TWTDL0_RX_TAG_SHFT       8
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TWTUL0_RX_TAG_ADDR       BN0_WF_ARB_TOP_D0PTR5_ADDR
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TWTUL0_RX_TAG_MASK       0x000000F0                // D0_WLAN_TWTUL0_RX_TAG[7..4]
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TWTUL0_RX_TAG_SHFT       4
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TWTTSFTF0_RX_TAG_ADDR    BN0_WF_ARB_TOP_D0PTR5_ADDR
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TWTTSFTF0_RX_TAG_MASK    0x0000000F                // D0_WLAN_TWTTSFTF0_RX_TAG[3..0]
#define BN0_WF_ARB_TOP_D0PTR5_D0_WLAN_TWTTSFTF0_RX_TAG_SHFT    0

/* =====================================================================================

  ---D0PTWR (0x820E3000 + 0x21C)---

    D0_SILENCE_WIN[14..0]        - (RW) In unit of 1us. HW will generate channel protect packet (base on D0_PTA_RW_MODE) when remaining window <= D0_SILENCE_WIN.
                                     (for DBDC channel 0)
    D0_BT_RW_OB_UNIT_MODE[15]    - (RW) The mode to select the resolution of BT released remaining/outband window.
                                     0: unit is 1us
                                     1: unit is 32us.
                                     (for DBDC channel 0)
    D0_PTA_RXACK_EARLY_EN[16]    - (RW) The WiFi receive ACK request early assertion enable signal.
                                     0: disable
                                     1: WF will early assert wifi_rx_req before TX ends.
                                     (for DBDC channel 0)
    D0_PTA_RXACK_EARLY_TIME[22..17] - (RW) The WiFi receive ACK request early assertion time before mac2phy_tx ends. The purpose is to cover the IDC interface and LTE-TX termination latency.
                                     The unit is 1us.
                                     (for DBDC channel 0)
    RESERVED23[23]               - (RO) Reserved bits
    D0_REQ_TIMEOUT[31..24]       - (RW) Used to specify the timeout for waiting WiFi_grant after asserting wifi_tx_req or wifi_rx_req.
                                     In unit of T (HW clock).
                                     0: if 0T no grant, request timeout
                                     1: if 1T no grant, request timeout
                                     ...
                                     255: if 255T no grant, request timeout
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTWR_D0_REQ_TIMEOUT_ADDR              BN0_WF_ARB_TOP_D0PTWR_ADDR
#define BN0_WF_ARB_TOP_D0PTWR_D0_REQ_TIMEOUT_MASK              0xFF000000                // D0_REQ_TIMEOUT[31..24]
#define BN0_WF_ARB_TOP_D0PTWR_D0_REQ_TIMEOUT_SHFT              24
#define BN0_WF_ARB_TOP_D0PTWR_D0_PTA_RXACK_EARLY_TIME_ADDR     BN0_WF_ARB_TOP_D0PTWR_ADDR
#define BN0_WF_ARB_TOP_D0PTWR_D0_PTA_RXACK_EARLY_TIME_MASK     0x007E0000                // D0_PTA_RXACK_EARLY_TIME[22..17]
#define BN0_WF_ARB_TOP_D0PTWR_D0_PTA_RXACK_EARLY_TIME_SHFT     17
#define BN0_WF_ARB_TOP_D0PTWR_D0_PTA_RXACK_EARLY_EN_ADDR       BN0_WF_ARB_TOP_D0PTWR_ADDR
#define BN0_WF_ARB_TOP_D0PTWR_D0_PTA_RXACK_EARLY_EN_MASK       0x00010000                // D0_PTA_RXACK_EARLY_EN[16]
#define BN0_WF_ARB_TOP_D0PTWR_D0_PTA_RXACK_EARLY_EN_SHFT       16
#define BN0_WF_ARB_TOP_D0PTWR_D0_BT_RW_OB_UNIT_MODE_ADDR       BN0_WF_ARB_TOP_D0PTWR_ADDR
#define BN0_WF_ARB_TOP_D0PTWR_D0_BT_RW_OB_UNIT_MODE_MASK       0x00008000                // D0_BT_RW_OB_UNIT_MODE[15]
#define BN0_WF_ARB_TOP_D0PTWR_D0_BT_RW_OB_UNIT_MODE_SHFT       15
#define BN0_WF_ARB_TOP_D0PTWR_D0_SILENCE_WIN_ADDR              BN0_WF_ARB_TOP_D0PTWR_ADDR
#define BN0_WF_ARB_TOP_D0PTWR_D0_SILENCE_WIN_MASK              0x00007FFF                // D0_SILENCE_WIN[14..0]
#define BN0_WF_ARB_TOP_D0PTWR_D0_SILENCE_WIN_SHFT              0

/* =====================================================================================

  ---D0RWPTCR0 (0x820E3000 + 0x220)---

    D0_AIFS_RWP[3..0]            - (RW) The same as AIFS_AC00.
                                     (for DBDC channel 0)
    RESERVED4[7..4]              - (RO) Reserved bits
    D0_CWMIN_RWP[12..8]          - (RW) The same as CWMIN_AC00.
                                     (for DBDC channel 0)
    RESERVED13[15..13]           - (RO) Reserved bits
    D0_CWMAX_RWP[20..16]         - (RW) The same as CWMAX_AC00.
                                     (for DBDC channel 0)
    RESERVED21[23..21]           - (RO) Reserved bits
    D0_CURR_CW_RWP[28..24]       - (RO) The same as CURR_CW_AC00.
                                     (for DBDC channel 0)
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_CURR_CW_RWP_ADDR           BN0_WF_ARB_TOP_D0RWPTCR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_CURR_CW_RWP_MASK           0x1F000000                // D0_CURR_CW_RWP[28..24]
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_CURR_CW_RWP_SHFT           24
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_CWMAX_RWP_ADDR             BN0_WF_ARB_TOP_D0RWPTCR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_CWMAX_RWP_MASK             0x001F0000                // D0_CWMAX_RWP[20..16]
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_CWMAX_RWP_SHFT             16
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_CWMIN_RWP_ADDR             BN0_WF_ARB_TOP_D0RWPTCR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_CWMIN_RWP_MASK             0x00001F00                // D0_CWMIN_RWP[12..8]
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_CWMIN_RWP_SHFT             8
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_AIFS_RWP_ADDR              BN0_WF_ARB_TOP_D0RWPTCR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_AIFS_RWP_MASK              0x0000000F                // D0_AIFS_RWP[3..0]
#define BN0_WF_ARB_TOP_D0RWPTCR0_D0_AIFS_RWP_SHFT              0

/* =====================================================================================

  ---D0RWPTCR1 (0x820E3000 + 0x224)---

    RESERVED0[7..0]              - (RO) Reserved bits
    D0_RWP_RETRY_LIMIT[11..8]    - (RW) Retry limit
                                     (for DBDC channel 0)
    RESERVED12[15..12]           - (RO) Reserved bits
    D0_RWP_EXTRA_RSVD[25..16]    - (RW) Except BT period, the D0_RWP_EXTRA_RSVD should add extra value ceil(D0_BT_PRE_REQ_TIME/32)
                                      In unit of 32 us
                                     (a) If CTS2Self mechanism is enabled, the exact reserved channel period is
                                     D0_RWP_EXTRA_DURATION + Silence window - elapsing time 
                                     (b) If "Fast PS Coexistence" is defined, this value is to add into the duration field of the QoS-Null frame that is transmitted at the starting time of silence window
                                     (for DBDC channel 0)
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RWPTCR1_D0_RWP_EXTRA_RSVD_ADDR        BN0_WF_ARB_TOP_D0RWPTCR1_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR1_D0_RWP_EXTRA_RSVD_MASK        0x03FF0000                // D0_RWP_EXTRA_RSVD[25..16]
#define BN0_WF_ARB_TOP_D0RWPTCR1_D0_RWP_EXTRA_RSVD_SHFT        16
#define BN0_WF_ARB_TOP_D0RWPTCR1_D0_RWP_RETRY_LIMIT_ADDR       BN0_WF_ARB_TOP_D0RWPTCR1_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR1_D0_RWP_RETRY_LIMIT_MASK       0x00000F00                // D0_RWP_RETRY_LIMIT[11..8]
#define BN0_WF_ARB_TOP_D0RWPTCR1_D0_RWP_RETRY_LIMIT_SHFT       8

/* =====================================================================================

  ---D0RWPTCR2 (0x820E3000 + 0x228)---

    D0_AC_SILENCE_WIN[14..0]     - (RW) In unit of 1us. All Tx queue will pause if remaining window less than D0_AC_SILENCE_WIN.
                                     (for DBDC channel 0)
    RESERVED15[15]               - (RO) Reserved bits
    D0_SILENCE_WIN_AIFS[19..16]  - (RW) All AC queue's AIFS when remain window less than silence window
                                     (for DBDC channel 0)
    RESERVED20[30..20]           - (RO) Reserved bits
    D0_SILENCE_WIN_NB_PS_EN[31]  - (RW) When D0_SILENCE_WIN_PS_EN, this field indicated the PS bit of non-bufferable packets modify or not.
                                     (only valid when D0_PTA_RW_MODE[4]=1)
                                      0: PS bit of non-bufferable packets is the same original define whether into silence window or not
                                      1: PS bit of non-bufferable packet is always 1 when remaining window less than silence window; PS bit is the same original define when remaining window more than silence window.
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RWPTCR2_D0_SILENCE_WIN_NB_PS_EN_ADDR  BN0_WF_ARB_TOP_D0RWPTCR2_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR2_D0_SILENCE_WIN_NB_PS_EN_MASK  0x80000000                // D0_SILENCE_WIN_NB_PS_EN[31]
#define BN0_WF_ARB_TOP_D0RWPTCR2_D0_SILENCE_WIN_NB_PS_EN_SHFT  31
#define BN0_WF_ARB_TOP_D0RWPTCR2_D0_SILENCE_WIN_AIFS_ADDR      BN0_WF_ARB_TOP_D0RWPTCR2_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR2_D0_SILENCE_WIN_AIFS_MASK      0x000F0000                // D0_SILENCE_WIN_AIFS[19..16]
#define BN0_WF_ARB_TOP_D0RWPTCR2_D0_SILENCE_WIN_AIFS_SHFT      16
#define BN0_WF_ARB_TOP_D0RWPTCR2_D0_AC_SILENCE_WIN_ADDR        BN0_WF_ARB_TOP_D0RWPTCR2_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR2_D0_AC_SILENCE_WIN_MASK        0x00007FFF                // D0_AC_SILENCE_WIN[14..0]
#define BN0_WF_ARB_TOP_D0RWPTCR2_D0_AC_SILENCE_WIN_SHFT        0

/* =====================================================================================

  ---D0RWPTCR3 (0x820E3000 + 0x22C)---

    D0_RWP_FRAME_RATE[5..0]      - (RW) This Field is used for CTS2Self and CF-END and QoS Null packet
                                      arb_cr_pta_frame_mode = 3'b000:
                                     CCK (long preamble)
                                     6'b00_0000: 1M
                                     6'b00_0001: 2M
                                     6'b00_0010: 5.5M
                                     6'b00_0011: 11M
                                     CCK (short preamble)
                                     6'b00_0101: 2M
                                     6'b00_0110: 5.5M
                                     6'b00_0111: 11M
                                      arb_cr_pta_frame_mode = 3'b001:
                                     Legacy OFDM:
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     arb_cr_pta_frame_mode =3'b010 or 3'b011HT rate:
                                     The bits 0~5 indicate MCSN, N=0~23 and 32, others reserved.
                                     
                                      arb_cr_pta_frame_mode =3'b100:
                                     reserved
                                     (for DBDC channel 0)
    RESERVED6[7..6]              - (RO) Reserved bits
    D0_RWP_FRAME_MODE[10..8]     - (RW) This Field is used for CTS2Self, CF-END and QoS Null packet
                                     This field indicates the mode of
                                     
                                     000: Legacy CCK
                                     001: Legacy OFDM
                                     010: HT Mixed mode
                                     011: HT Green field mode
                                     Others: meaningless
                                     (for DBDC channel 0)
    D0_RWP_FRAME_SPE_IDX[15..11] - (RW) This Field is used for CTS2Self, CF-END and QoS Null packet
                                     This field indicates spatial exension index.
                                     (for DBDC channel 0)
    D0_RWP_FRAME_ANT_ID[27..16]  - (RW) This Field is used for CTS2Self, CF-END and QoS Null packet
                                     This field indicates smart antenna index.
                                     (for DBDC channel 0)
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_ANT_ID_ADDR      BN0_WF_ARB_TOP_D0RWPTCR3_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_ANT_ID_MASK      0x0FFF0000                // D0_RWP_FRAME_ANT_ID[27..16]
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_ANT_ID_SHFT      16
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_SPE_IDX_ADDR     BN0_WF_ARB_TOP_D0RWPTCR3_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_SPE_IDX_MASK     0x0000F800                // D0_RWP_FRAME_SPE_IDX[15..11]
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_SPE_IDX_SHFT     11
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_MODE_ADDR        BN0_WF_ARB_TOP_D0RWPTCR3_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_MODE_MASK        0x00000700                // D0_RWP_FRAME_MODE[10..8]
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_MODE_SHFT        8
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_RATE_ADDR        BN0_WF_ARB_TOP_D0RWPTCR3_ADDR
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_RATE_MASK        0x0000003F                // D0_RWP_FRAME_RATE[5..0]
#define BN0_WF_ARB_TOP_D0RWPTCR3_D0_RWP_FRAME_RATE_SHFT        0

/* =====================================================================================

  ---D0RWPCR (0x820E3000 + 0x230)---

    D0_FDD_HT40_RW_GUARD[7..0]   - (RW) Guard Time for FDD HT40 Remaining Window feature. When ARB Remaining Window is less than Guard time, AGG is only allowed to choose BW20 to sent out packet. Unit is 32us.
                                     Notice: 0 is illegal, at least set to 1
    RESERVED8[14..8]             - (RO) Reserved bits
    D0_FDD_HT40_RW_EN[15]        - (RW) Enable for FDD HT40 Remaining Window feature.
                                     0: Disable
                                     1: Enable
    RESERVED16[21..16]           - (RO) Reserved bits
    D0_PSON_MAXREMWIN_EN[22]     - (RW) PSON transmit don't honor remaining window
                                     0: PSON transmit as normal
                                     1: PSON transmit don't honor remaining window
                                     (for DBDC channel 0)
    D0_CTS_MAXREMWIN_EN[23]      - (RW) CTS2Self transmit don't honor remaining window
                                     0: CTS2Self transmit as normal
                                     1: CTS2Self transmit don't honor remaining window
                                     (for DBDC channel 0)
    D0_CTS_REISSUE_EARLY_TIME[30..24] - (RW) Only valid when D0_CTS_REISSUE_EN=1.
                                     The unit is 64us.
                                     HW will automatically reissue a CTS2SELF when remaining TXOP is less than CTS_REISSUE_EARLY_TIME and remaining window is less than silence window.
                                     (for DBDC channel 0)
    D0_CTS_REISSUE_EN[31]        - (RW) CTS2SELF automatically reissue enable
                                     0: disable
                                     1: enable
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RWPCR_D0_CTS_REISSUE_EN_ADDR          BN0_WF_ARB_TOP_D0RWPCR_ADDR
#define BN0_WF_ARB_TOP_D0RWPCR_D0_CTS_REISSUE_EN_MASK          0x80000000                // D0_CTS_REISSUE_EN[31]
#define BN0_WF_ARB_TOP_D0RWPCR_D0_CTS_REISSUE_EN_SHFT          31
#define BN0_WF_ARB_TOP_D0RWPCR_D0_CTS_REISSUE_EARLY_TIME_ADDR  BN0_WF_ARB_TOP_D0RWPCR_ADDR
#define BN0_WF_ARB_TOP_D0RWPCR_D0_CTS_REISSUE_EARLY_TIME_MASK  0x7F000000                // D0_CTS_REISSUE_EARLY_TIME[30..24]
#define BN0_WF_ARB_TOP_D0RWPCR_D0_CTS_REISSUE_EARLY_TIME_SHFT  24
#define BN0_WF_ARB_TOP_D0RWPCR_D0_CTS_MAXREMWIN_EN_ADDR        BN0_WF_ARB_TOP_D0RWPCR_ADDR
#define BN0_WF_ARB_TOP_D0RWPCR_D0_CTS_MAXREMWIN_EN_MASK        0x00800000                // D0_CTS_MAXREMWIN_EN[23]
#define BN0_WF_ARB_TOP_D0RWPCR_D0_CTS_MAXREMWIN_EN_SHFT        23
#define BN0_WF_ARB_TOP_D0RWPCR_D0_PSON_MAXREMWIN_EN_ADDR       BN0_WF_ARB_TOP_D0RWPCR_ADDR
#define BN0_WF_ARB_TOP_D0RWPCR_D0_PSON_MAXREMWIN_EN_MASK       0x00400000                // D0_PSON_MAXREMWIN_EN[22]
#define BN0_WF_ARB_TOP_D0RWPCR_D0_PSON_MAXREMWIN_EN_SHFT       22
#define BN0_WF_ARB_TOP_D0RWPCR_D0_FDD_HT40_RW_EN_ADDR          BN0_WF_ARB_TOP_D0RWPCR_ADDR
#define BN0_WF_ARB_TOP_D0RWPCR_D0_FDD_HT40_RW_EN_MASK          0x00008000                // D0_FDD_HT40_RW_EN[15]
#define BN0_WF_ARB_TOP_D0RWPCR_D0_FDD_HT40_RW_EN_SHFT          15
#define BN0_WF_ARB_TOP_D0RWPCR_D0_FDD_HT40_RW_GUARD_ADDR       BN0_WF_ARB_TOP_D0RWPCR_ADDR
#define BN0_WF_ARB_TOP_D0RWPCR_D0_FDD_HT40_RW_GUARD_MASK       0x000000FF                // D0_FDD_HT40_RW_GUARD[7..0]
#define BN0_WF_ARB_TOP_D0RWPCR_D0_FDD_HT40_RW_GUARD_SHFT       0

/* =====================================================================================

  ---D0RWPCFR0 (0x820E3000 + 0x234)---

    D0_RX_FRAMETIME_TH[10..0]    - (RW) The frame time threshold of the received packet.
                                     The unit is 32us.
                                     When the frame time of the received packet is larger than the threshold, it is regarded as long packet . When arb_cr_longpkt_protect_en=1, will do extra pta protect by change priority tag.
                                     (for DBDC channel 0)
    RESERVED11[11]               - (RO) Reserved bits
    D0_RX_NSW_TAG2[15..12]       - (RW) This field is used to indicate the tag of RX_PE/CCA/CCA_CS/mdrdy asserted to PTA once the long packet protection condition was hit.
                                     (for DBDC channel 0)
    D0_LONGPKT_PROTECT_EN[16]    - (RW) Rx long packet high priority enable.
                                     0: disable
                                     1: enable coex extra protect for the received long packet by change priority tag. Once  enable, ARB also inform RMAC to calculate the PPDU time
                                     (for DBDC channel 0)
    D0_LONGPKT_PROTECT_MODE[17]  - (RW) Rx long packet high priority mode.
                                     0: WF use lower priority firstly, and increase importance when receiving long packet.
                                     1: WF use higher priority firstly, and decrease importance when received packet is no need in protection.
                                     (for DBDC channel 0)
    D0_MDRDY_PPDUTIME_INT_EN[18] - (RW) Indicate if enable RMAC calculate PPDU Time and have interrupt or not.
                                     0: Disable RMAC PPDU time calculation and no interrupt.
                                     1: Enable RMAC to calculate the PPDU time of the mdrdy packet. If the PPDU time is larger than the D0_RX_FRAMETIME_TH, a interrupt named wf_arb_mdrdy_ppdutime_int (WIS2R bit20 in INT_WAKEUP CR) will be assert. Besides, the PPDU time of this received packet can be accessed in RQPTCR1.
                                     (for DBDC channel 0)
    D0_DIS_RX_REQ_INSCO_EN[19]   - (RW) Disable NSW PTA Rx request in SCO period.
                                     0: Disable this scheme.
                                     1: Forcefully disable wf_rx_req when the mdrdy is overlap with BT SCO period if the RA of mdrdy packet is not equal to our MAC0, MAC1, MAC2 address.
                                     (for DBDC channel 0)
    D0_TX_RWP_INSCO_EN[20]       - (RW) Remaining window protect can Tx in SCO period.
                                     0: Disable this scheme.
                                     1: Enable the capability of transmit RWP in BT SCO period. When this bit is enable, RWP should be issued at least once unless the remaining window suddenly becomes large.
                                     (for DBDC channel 0)
    D0_TX_RWP_STATISTIC_EN[21]   - (RW) Remaining window protect statistic enable.
                                     0: Disable this scheme.
                                     1: ARB will give arb_tx_rwp_need_pu and arb_tx_rwp_fail_pu to MIB module. Access MSDR35 of MIB CR can get the statistic values.
                                     (for DBDC channel 0)
    D0_RW0_NO_ACK_EN[22]         - (RW) Control TMAC response ACK or not when remaining window is 0.
                                     0: Tx Ack may issue even when there is no remaining window.
                                     1: Disable Tx Ack within the period of no remaining window.
                                     (for DBDC channel 0)
    RESERVED23[31..23]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_RW0_NO_ACK_EN_ADDR         BN0_WF_ARB_TOP_D0RWPCFR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_RW0_NO_ACK_EN_MASK         0x00400000                // D0_RW0_NO_ACK_EN[22]
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_RW0_NO_ACK_EN_SHFT         22
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_TX_RWP_STATISTIC_EN_ADDR   BN0_WF_ARB_TOP_D0RWPCFR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_TX_RWP_STATISTIC_EN_MASK   0x00200000                // D0_TX_RWP_STATISTIC_EN[21]
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_TX_RWP_STATISTIC_EN_SHFT   21
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_TX_RWP_INSCO_EN_ADDR       BN0_WF_ARB_TOP_D0RWPCFR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_TX_RWP_INSCO_EN_MASK       0x00100000                // D0_TX_RWP_INSCO_EN[20]
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_TX_RWP_INSCO_EN_SHFT       20
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_DIS_RX_REQ_INSCO_EN_ADDR   BN0_WF_ARB_TOP_D0RWPCFR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_DIS_RX_REQ_INSCO_EN_MASK   0x00080000                // D0_DIS_RX_REQ_INSCO_EN[19]
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_DIS_RX_REQ_INSCO_EN_SHFT   19
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_MDRDY_PPDUTIME_INT_EN_ADDR BN0_WF_ARB_TOP_D0RWPCFR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_MDRDY_PPDUTIME_INT_EN_MASK 0x00040000                // D0_MDRDY_PPDUTIME_INT_EN[18]
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_MDRDY_PPDUTIME_INT_EN_SHFT 18
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_LONGPKT_PROTECT_MODE_ADDR  BN0_WF_ARB_TOP_D0RWPCFR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_LONGPKT_PROTECT_MODE_MASK  0x00020000                // D0_LONGPKT_PROTECT_MODE[17]
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_LONGPKT_PROTECT_MODE_SHFT  17
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_LONGPKT_PROTECT_EN_ADDR    BN0_WF_ARB_TOP_D0RWPCFR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_LONGPKT_PROTECT_EN_MASK    0x00010000                // D0_LONGPKT_PROTECT_EN[16]
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_LONGPKT_PROTECT_EN_SHFT    16
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_RX_NSW_TAG2_ADDR           BN0_WF_ARB_TOP_D0RWPCFR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_RX_NSW_TAG2_MASK           0x0000F000                // D0_RX_NSW_TAG2[15..12]
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_RX_NSW_TAG2_SHFT           12
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_RX_FRAMETIME_TH_ADDR       BN0_WF_ARB_TOP_D0RWPCFR0_ADDR
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_RX_FRAMETIME_TH_MASK       0x000007FF                // D0_RX_FRAMETIME_TH[10..0]
#define BN0_WF_ARB_TOP_D0RWPCFR0_D0_RX_FRAMETIME_TH_SHFT       0

/* =====================================================================================

  ---D0RWPCFR1 (0x820E3000 + 0x238)---

    D0_MDRDY_PPDUTIME[15..0]     - (RO) The PPDU time of the mdrdy packet which is larger than the CR programmed threshold (rx_frametime_th in D0RWPCFR0).
                                     (for DBDC channel 0)
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RWPCFR1_D0_MDRDY_PPDUTIME_ADDR        BN0_WF_ARB_TOP_D0RWPCFR1_ADDR
#define BN0_WF_ARB_TOP_D0RWPCFR1_D0_MDRDY_PPDUTIME_MASK        0x0000FFFF                // D0_MDRDY_PPDUTIME[15..0]
#define BN0_WF_ARB_TOP_D0RWPCFR1_D0_MDRDY_PPDUTIME_SHFT        0

/* =====================================================================================

  ---D0RPTDD0 (0x820E3000 + 0x23C)---

    D0_WL_PROT_TAG[3..0]         - (RW) This field is used for priority tag when triggering protection mechanism is enabled
                                     (for DBDC channel 0)
    RESERVED4[7..4]              - (RO) Reserved bits
    D0_WL_PROT_ELY_CS_TO_CNT[15..8] - (RW) This field is used for duration threshold of duration protection for non-no-data packet type; its unit is 32 us.
                                     This field is used for Timeout counter from CTS send out to CS is detected. If CS not asserted within the Timeout value, wifi_rx_req will be de-asserted. (in unit of us, default set 20us)
                                     (for DBDC channel 0)
    D0_WL_LPKT_DATA_DUR_THD[26..16] - (RW) This field is used for duration threshold of duration protection for non-no-data packet type; its unit is 32 us.
                                     (for DBDC channel 0)
    D0_WL_PROT_LEGACY_EN[27]     - (RW) This field is used for legacy or new protection mechanism.
                                     0: Use new duration and rate protection.
                                     1: Use legacy duration protection by ARB_RWPCFR0.
                                     (for DBDC channel 0)
    D0_WL_PROT_RTS_EN[28]        - (RW) This field is used for enable RTS packet type protection.
                                     (for DBDC channel 0)
    D0_WL_PROT_ELY_RX_REQ_EN[29] - (RW) This field is used for Enable early Rx request after Rx RTS and Tx CTS for a number of slot idle counter duration.
                                     (for DBDC channel 0)
    D0_WL_LRATE_EN[30]           - (RW) This field is used for enable non-no-data rate protection
                                     (for DBDC channel 0)
    D0_WL_LPKT_EN[31]            - (RW) This field is used for enable non-no-data duration protection.
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_LPKT_EN_ADDR             BN0_WF_ARB_TOP_D0RPTDD0_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_LPKT_EN_MASK             0x80000000                // D0_WL_LPKT_EN[31]
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_LPKT_EN_SHFT             31
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_LRATE_EN_ADDR            BN0_WF_ARB_TOP_D0RPTDD0_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_LRATE_EN_MASK            0x40000000                // D0_WL_LRATE_EN[30]
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_LRATE_EN_SHFT            30
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_ELY_RX_REQ_EN_ADDR  BN0_WF_ARB_TOP_D0RPTDD0_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_ELY_RX_REQ_EN_MASK  0x20000000                // D0_WL_PROT_ELY_RX_REQ_EN[29]
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_ELY_RX_REQ_EN_SHFT  29
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_RTS_EN_ADDR         BN0_WF_ARB_TOP_D0RPTDD0_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_RTS_EN_MASK         0x10000000                // D0_WL_PROT_RTS_EN[28]
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_RTS_EN_SHFT         28
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_LEGACY_EN_ADDR      BN0_WF_ARB_TOP_D0RPTDD0_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_LEGACY_EN_MASK      0x08000000                // D0_WL_PROT_LEGACY_EN[27]
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_LEGACY_EN_SHFT      27
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_LPKT_DATA_DUR_THD_ADDR   BN0_WF_ARB_TOP_D0RPTDD0_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_LPKT_DATA_DUR_THD_MASK   0x07FF0000                // D0_WL_LPKT_DATA_DUR_THD[26..16]
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_LPKT_DATA_DUR_THD_SHFT   16
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_ELY_CS_TO_CNT_ADDR  BN0_WF_ARB_TOP_D0RPTDD0_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_ELY_CS_TO_CNT_MASK  0x0000FF00                // D0_WL_PROT_ELY_CS_TO_CNT[15..8]
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_ELY_CS_TO_CNT_SHFT  8
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_TAG_ADDR            BN0_WF_ARB_TOP_D0RPTDD0_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_TAG_MASK            0x0000000F                // D0_WL_PROT_TAG[3..0]
#define BN0_WF_ARB_TOP_D0RPTDD0_D0_WL_PROT_TAG_SHFT            0

/* =====================================================================================

  ---D0RPTDD1 (0x820E3000 + 0x240)---

    D0_WL_LPKT_PROT_CNT[7..0]    - (RW) This field is used for Trigger counter to enable duration protection
                                     (for DBDC channel 0)
    D0_WL_LPKT_RETURN_CNT[15..8] - (RW) This field is used for return counter to disable duration protection, 0xFF means never disable.
                                     (for DBDC channel 0)
    D0_WL_LRATE_PROT_CNT[23..16] - (RW) This field is used for Trigger counter to enable rate protection
                                     (for DBDC channel 0)
    D0_WL_LRATE_RETURN_CNT[31..24] - (RW) This field is used for return counter to disable rate protection, 0xFF means never disable.
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LRATE_RETURN_CNT_ADDR    BN0_WF_ARB_TOP_D0RPTDD1_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LRATE_RETURN_CNT_MASK    0xFF000000                // D0_WL_LRATE_RETURN_CNT[31..24]
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LRATE_RETURN_CNT_SHFT    24
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LRATE_PROT_CNT_ADDR      BN0_WF_ARB_TOP_D0RPTDD1_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LRATE_PROT_CNT_MASK      0x00FF0000                // D0_WL_LRATE_PROT_CNT[23..16]
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LRATE_PROT_CNT_SHFT      16
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LPKT_RETURN_CNT_ADDR     BN0_WF_ARB_TOP_D0RPTDD1_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LPKT_RETURN_CNT_MASK     0x0000FF00                // D0_WL_LPKT_RETURN_CNT[15..8]
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LPKT_RETURN_CNT_SHFT     8
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LPKT_PROT_CNT_ADDR       BN0_WF_ARB_TOP_D0RPTDD1_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LPKT_PROT_CNT_MASK       0x000000FF                // D0_WL_LPKT_PROT_CNT[7..0]
#define BN0_WF_ARB_TOP_D0RPTDD1_D0_WL_LPKT_PROT_CNT_SHFT       0

/* =====================================================================================

  ---D0RPTDD2 (0x820E3000 + 0x244)---

    D0_CCK_LRATE_DATA_THD[1..0]  - (RW) This field is used for CCK threshold of rate protection for non-no-data packet type.
                                     2'b00: 1M
                                     2'b01: 2M
                                     2'b10: 5.5M
                                     2'b11: 11M
                                     (for DBDC channel 0)
    D0_OFDM_LRATE_DATA_THD[5..2] - (RW) This field is used for OFDM threshold of rate protection for non-no-data packet type. RX OFDM rate will be re-decoded to as following:
                                     4'b1000: 6M
                                     4'b1001: 9M
                                     4'b1010:12M
                                     4'b1011:18M
                                     4'b1100:24M
                                     4'b1101:36M
                                     4'b1110:48M
                                     4'b1111:54M
                                     (for DBDC channel 0)
    RESERVED6[15..6]             - (RO) Reserved bits
    D0_CCK_LRATE_RTS_THD[17..16] - (RW) This field is used for CCK threshold of rate protection for RTS packet type. (Usage same as D0_CCK_LRATE_DATA_THD)
                                     (for DBDC channel 0)
    D0_OFDM_LRATE_RTS_THD[21..18] - (RW) This field is used for OFDM threshold of rate protection for RTS packet type (Usage same as D0_OFDM_LRATE_DATA_THD)
                                     (for DBDC channel 0)
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_OFDM_LRATE_RTS_THD_ADDR     BN0_WF_ARB_TOP_D0RPTDD2_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_OFDM_LRATE_RTS_THD_MASK     0x003C0000                // D0_OFDM_LRATE_RTS_THD[21..18]
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_OFDM_LRATE_RTS_THD_SHFT     18
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_CCK_LRATE_RTS_THD_ADDR      BN0_WF_ARB_TOP_D0RPTDD2_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_CCK_LRATE_RTS_THD_MASK      0x00030000                // D0_CCK_LRATE_RTS_THD[17..16]
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_CCK_LRATE_RTS_THD_SHFT      16
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_OFDM_LRATE_DATA_THD_ADDR    BN0_WF_ARB_TOP_D0RPTDD2_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_OFDM_LRATE_DATA_THD_MASK    0x0000003C                // D0_OFDM_LRATE_DATA_THD[5..2]
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_OFDM_LRATE_DATA_THD_SHFT    2
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_CCK_LRATE_DATA_THD_ADDR     BN0_WF_ARB_TOP_D0RPTDD2_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_CCK_LRATE_DATA_THD_MASK     0x00000003                // D0_CCK_LRATE_DATA_THD[1..0]
#define BN0_WF_ARB_TOP_D0RPTDD2_D0_CCK_LRATE_DATA_THD_SHFT     0

/* =====================================================================================

  ---D0RPTDD3 (0x820E3000 + 0x248)---

    D0_WL_PROT_COMB_HIT_CNT[15..0] - (RO) This field is used for Protection counter (combination from both long pkt and low rate) to record how many times that Wi-Fi priority tag was updated as wl_protect_tag, it'll wrap around when reaches the maximum value.
                                     (for DBDC channel 0)
    D0_WL_PROT_ELY_MDRDY_TO_CNT[23..16] - (RW) This field is used for Timeout counter from CS is detected to MDRDY is asserted. If MDRDY not asserted within the Timeout value, wifi_rx_req will be de-asserted. (in unit of us, default set 192us)
                                     (for DBDC channel 0)
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RPTDD3_D0_WL_PROT_ELY_MDRDY_TO_CNT_ADDR BN0_WF_ARB_TOP_D0RPTDD3_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD3_D0_WL_PROT_ELY_MDRDY_TO_CNT_MASK 0x00FF0000                // D0_WL_PROT_ELY_MDRDY_TO_CNT[23..16]
#define BN0_WF_ARB_TOP_D0RPTDD3_D0_WL_PROT_ELY_MDRDY_TO_CNT_SHFT 16
#define BN0_WF_ARB_TOP_D0RPTDD3_D0_WL_PROT_COMB_HIT_CNT_ADDR   BN0_WF_ARB_TOP_D0RPTDD3_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD3_D0_WL_PROT_COMB_HIT_CNT_MASK   0x0000FFFF                // D0_WL_PROT_COMB_HIT_CNT[15..0]
#define BN0_WF_ARB_TOP_D0RPTDD3_D0_WL_PROT_COMB_HIT_CNT_SHFT   0

/* =====================================================================================

  ---D0SXCR0 (0x820E3000 + 0x24C)---

    D0_PTA_SX_MAN_MODE[0]        - (RW) SX select manual mode
                                     0: disable
                                     1: enable
                                     (for DBDC channel 0)
    D0_SW_PTA_SX_SEL[1]          - (RW) Only valid when D0_PTA_SX_MAN_MODE=1.
                                     0: SX grant to WiFi
                                     1: SX grant to BT.
                                     (for DBDC channel 0)
    RESERVED2[3..2]              - (RO) Reserved bits
    D0_TX_SX_ABORT_MODE[4]       - (RW) The period qualified by SX ready signal.
                                     0: tmac_tx_active_win (should be coverd by mac2phy_tx)
                                     We issue a abort when  tmac_tx_active_win & (~wf_sx_ready)
                                     1: mac2phy_tx
                                     We issue a abort when  mac2phy_tx & (~wf_sx_ready)
                                     (for DBDC channel 0)
    D0_AGG_SX_READY_MODE[5]      - (RW) The mode to choose which signal should be qualified by AGG. When during TXOP, AGG should not do retry when arb_agg_wf_sx_ready is equal to 0.
                                     0: arb_agg_wf_sx_ready = wf_sx_pre_ready
                                     1: arb_agg_wf_sx_ready = wf_sx_ready
                                     (for DBDC channel 0)
    D0_AC_REQ_EXTRA_DIS[6]       - (RW) To disable arb_req_extra signal to assert wifi_tx_req or wifi_rx_req
                                     0: enable 
                                     1: disable (compatible to designs before MT6628)
                                     (for DBDC channel 0)
    D0_AC_REQ_EXTRA_MODE[7]      - (RW) The mode to indicate txreq or rxreq to assertion for taking SX using right.
                                     0: assert wifi_tx_req
                                     1: assert wifi_rx_req
                                     (for DBDC channel 0)
    D0_SW_VERIFY_CNT_EN[8]       - (RW) It is a switch to enable D0_WF_REQ_TIME_CNT and D0_WF_TX_ABORT_CNT
                                     0: disable
                                     1: enable
                                     (for DBDC channel 0)
    RESERVED9[23..9]             - (RO) Reserved bits
    D0_BT_PRE_REQ_TIME[29..24]   - (RW) The time of BT pre-assertion PTA request in 1us unit.
                                     It means WF actual usable remaining window is BT released remaining window minus D0_BT_PRE_REQ_TIME.
                                     (for DBDC channel 0)
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0SXCR0_D0_BT_PRE_REQ_TIME_ADDR         BN0_WF_ARB_TOP_D0SXCR0_ADDR
#define BN0_WF_ARB_TOP_D0SXCR0_D0_BT_PRE_REQ_TIME_MASK         0x3F000000                // D0_BT_PRE_REQ_TIME[29..24]
#define BN0_WF_ARB_TOP_D0SXCR0_D0_BT_PRE_REQ_TIME_SHFT         24
#define BN0_WF_ARB_TOP_D0SXCR0_D0_SW_VERIFY_CNT_EN_ADDR        BN0_WF_ARB_TOP_D0SXCR0_ADDR
#define BN0_WF_ARB_TOP_D0SXCR0_D0_SW_VERIFY_CNT_EN_MASK        0x00000100                // D0_SW_VERIFY_CNT_EN[8]
#define BN0_WF_ARB_TOP_D0SXCR0_D0_SW_VERIFY_CNT_EN_SHFT        8
#define BN0_WF_ARB_TOP_D0SXCR0_D0_AC_REQ_EXTRA_MODE_ADDR       BN0_WF_ARB_TOP_D0SXCR0_ADDR
#define BN0_WF_ARB_TOP_D0SXCR0_D0_AC_REQ_EXTRA_MODE_MASK       0x00000080                // D0_AC_REQ_EXTRA_MODE[7]
#define BN0_WF_ARB_TOP_D0SXCR0_D0_AC_REQ_EXTRA_MODE_SHFT       7
#define BN0_WF_ARB_TOP_D0SXCR0_D0_AC_REQ_EXTRA_DIS_ADDR        BN0_WF_ARB_TOP_D0SXCR0_ADDR
#define BN0_WF_ARB_TOP_D0SXCR0_D0_AC_REQ_EXTRA_DIS_MASK        0x00000040                // D0_AC_REQ_EXTRA_DIS[6]
#define BN0_WF_ARB_TOP_D0SXCR0_D0_AC_REQ_EXTRA_DIS_SHFT        6
#define BN0_WF_ARB_TOP_D0SXCR0_D0_AGG_SX_READY_MODE_ADDR       BN0_WF_ARB_TOP_D0SXCR0_ADDR
#define BN0_WF_ARB_TOP_D0SXCR0_D0_AGG_SX_READY_MODE_MASK       0x00000020                // D0_AGG_SX_READY_MODE[5]
#define BN0_WF_ARB_TOP_D0SXCR0_D0_AGG_SX_READY_MODE_SHFT       5
#define BN0_WF_ARB_TOP_D0SXCR0_D0_TX_SX_ABORT_MODE_ADDR        BN0_WF_ARB_TOP_D0SXCR0_ADDR
#define BN0_WF_ARB_TOP_D0SXCR0_D0_TX_SX_ABORT_MODE_MASK        0x00000010                // D0_TX_SX_ABORT_MODE[4]
#define BN0_WF_ARB_TOP_D0SXCR0_D0_TX_SX_ABORT_MODE_SHFT        4
#define BN0_WF_ARB_TOP_D0SXCR0_D0_SW_PTA_SX_SEL_ADDR           BN0_WF_ARB_TOP_D0SXCR0_ADDR
#define BN0_WF_ARB_TOP_D0SXCR0_D0_SW_PTA_SX_SEL_MASK           0x00000002                // D0_SW_PTA_SX_SEL[1]
#define BN0_WF_ARB_TOP_D0SXCR0_D0_SW_PTA_SX_SEL_SHFT           1
#define BN0_WF_ARB_TOP_D0SXCR0_D0_PTA_SX_MAN_MODE_ADDR         BN0_WF_ARB_TOP_D0SXCR0_ADDR
#define BN0_WF_ARB_TOP_D0SXCR0_D0_PTA_SX_MAN_MODE_MASK         0x00000001                // D0_PTA_SX_MAN_MODE[0]
#define BN0_WF_ARB_TOP_D0SXCR0_D0_PTA_SX_MAN_MODE_SHFT         0

/* =====================================================================================

  ---D0SXCR1 (0x820E3000 + 0x250)---

    D0_REQ_BF_TH[3..0]           - (RW) The pre wf_rx_req assertion timing which is in advance (D0_REQ_BF_TH*slot_time) before really TX time.
                                     General suggested setting:
                                      (SX settle time+X) < one slot time: 0
                                      (SX settle time+X) >= one slot time: ceil((settle time+X)/slot time) 
                                      X is 1 when D0_TX_SX_ABORT_MODE = 0
                                      X is 3 when D0_TX_SX_ABORT_MODE = 1
                                     (for DBDC channel 0)
    RESERVED4[5..4]              - (RO) Reserved bits
    D0_SX_SETTLE_CNT_RST[6]      - (RW) A reset signal to reset the 6-bit counter which start to increase if SX is for WF and reset to 0 if SX is for BT.
                                     0: no reset
                                     1: generate a pulse to reset the counter value to 6'h0.
    D0_SX_SETTLE_CNT_EN[7]       - (RW) The switch to decide if the settle counter value is used or not.
                                     0: the signals to indicate SX_CCA_SETTLE, SX_PRE_SETTLE, and SX_SETTLE are always be 1.
                                     1: the signals to indicate SX_CCA_SETTLE, SX_PRE_SETTLE, and SX_SETTLE should depend on the settle counter value. 
                                     (for DBDC channel 0)
    D0_SX_SETTLE_TIME[13..8]     - (RW) The SX settle time in 1us unit.
                                     It means the SX actual settle time.
                                     The purpose is to abort TX packet if SX is not settle done.
                                     (for DBDC channel 0)
    RESERVED14[15..14]           - (RO) Reserved bits
    D0_SX_PRE_SETTLE_TIME[21..16] - (RW) The pre SX settle time in 1us unit.
                                     It means ARB can prepare to Tx packet after D0_SX_PRE_SETTLE_TIME us if SX switches from BT to WF.
                                     General suggested setting = D0_SX_SETTLE_TIME - slot_time
                                     (for DBDC channel 0)
    RESERVED22[23..22]           - (RO) Reserved bits
    D0_SX_CCA_SETTLE_TIME[29..24] - (RW) The CCA SX settle time in 1us unit.
                                     It means mac2phy_rx can enable PHY to receive after D0_SX_CCA_SETTLE_TIME us if SX switches from BT to WF.
                                     The purpose is to prevent CCA false alarm if the ppm of SX is not under a save value (e.g. 400ppm).
                                     (for DBDC channel 0)
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_CCA_SETTLE_TIME_ADDR      BN0_WF_ARB_TOP_D0SXCR1_ADDR
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_CCA_SETTLE_TIME_MASK      0x3F000000                // D0_SX_CCA_SETTLE_TIME[29..24]
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_CCA_SETTLE_TIME_SHFT      24
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_PRE_SETTLE_TIME_ADDR      BN0_WF_ARB_TOP_D0SXCR1_ADDR
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_PRE_SETTLE_TIME_MASK      0x003F0000                // D0_SX_PRE_SETTLE_TIME[21..16]
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_PRE_SETTLE_TIME_SHFT      16
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_SETTLE_TIME_ADDR          BN0_WF_ARB_TOP_D0SXCR1_ADDR
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_SETTLE_TIME_MASK          0x00003F00                // D0_SX_SETTLE_TIME[13..8]
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_SETTLE_TIME_SHFT          8
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_SETTLE_CNT_EN_ADDR        BN0_WF_ARB_TOP_D0SXCR1_ADDR
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_SETTLE_CNT_EN_MASK        0x00000080                // D0_SX_SETTLE_CNT_EN[7]
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_SETTLE_CNT_EN_SHFT        7
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_SETTLE_CNT_RST_ADDR       BN0_WF_ARB_TOP_D0SXCR1_ADDR
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_SETTLE_CNT_RST_MASK       0x00000040                // D0_SX_SETTLE_CNT_RST[6]
#define BN0_WF_ARB_TOP_D0SXCR1_D0_SX_SETTLE_CNT_RST_SHFT       6
#define BN0_WF_ARB_TOP_D0SXCR1_D0_REQ_BF_TH_ADDR               BN0_WF_ARB_TOP_D0SXCR1_ADDR
#define BN0_WF_ARB_TOP_D0SXCR1_D0_REQ_BF_TH_MASK               0x0000000F                // D0_REQ_BF_TH[3..0]
#define BN0_WF_ARB_TOP_D0SXCR1_D0_REQ_BF_TH_SHFT               0

/* =====================================================================================

  ---D0SXCR2 (0x820E3000 + 0x254)---

    D0_WF_REQ_TIME_CNT[7..0]     - (RO) The unit is 1us.
                                     A counter to count up starts from wf_tx_req or wf_rx_req rising and ends by tmac_tx_active (or mac2phy_tx) rising. Besides, the counter  reset to 0 when 
                                     1. Set WF_REQ_TIME_RST=1
                                     2. Neither wf_tx_req nor wf_rx_req
                                     3. Tx abort
                                     (for DBDC channel 0)
    D0_WF_REQ_TIME_RST[8]        - (W1C) A reset signal to reset the 8-bit statistic counter D0_WF_REQ_TIME_STATISTIC.
                                     0: no reset
                                     1: generate a pulse to reset the counter value to 8'h0.
                                     (for DBDC channel 0)
    RESERVED9[11..9]             - (RO) Reserved bits
    D0_WF_TX_ABORT_CNT[15..12]   - (RO) Only valid when D0_SW_VERIFY_CNT_EN = 1.
                                     It means the number of TX abort happened and it reset to 0 when D0_WF_REQ_TIME_RST = 1.
                                     (for DBDC channel 0)
    RESERVED16[19..16]           - (RO) Reserved bits
    D0_PTA_SX_SEL_SYNC[20]       - (RO) The sync. phase of pta_sx_sel_pck (D0_DIG_PTA_SX_SEL mux with WS_PTA_SX_SEL)
                                     0: SX grant to WiFi
                                     1: SX grant to BT.
                                     (for DBDC channel 0)
    D0_WF_SX_READY[21]           - (RO) It means if D0_SX_SETTLE_CNT>= D0_SX_SETTLE_TIME or not
                                     (for DBDC channel 0)
    D0_WF_SX_PRE_READY[22]       - (RO) It means if D0_SX_SETTLE_CNT>= D0_SX_PRE_SETTLE_TIME or not
                                     (for DBDC channel 0)
    D0_WF_SX_CCA_READY[23]       - (RO) It means if D0_SX_SETTLE_CNT>= D0_SX_CCA_SETTLE_TIME or not
                                     (for DBDC channel 0)
    D0_SX_SETTLE_CNT[29..24]     - (RO) The SX settle counter which unit is 1 us.
                                     To calculate the time start from D0_PTA_SX_SEL_SYNC falling edge.
                                     (for DBDC channel 0)
    D0_DIG_PTA_SX_SEL[30]        - (RO) SX selection signal from PTA.
                                     0: select WF
                                     1: select BT
                                     (for DBDC channel 0)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0SXCR2_D0_DIG_PTA_SX_SEL_ADDR          BN0_WF_ARB_TOP_D0SXCR2_ADDR
#define BN0_WF_ARB_TOP_D0SXCR2_D0_DIG_PTA_SX_SEL_MASK          0x40000000                // D0_DIG_PTA_SX_SEL[30]
#define BN0_WF_ARB_TOP_D0SXCR2_D0_DIG_PTA_SX_SEL_SHFT          30
#define BN0_WF_ARB_TOP_D0SXCR2_D0_SX_SETTLE_CNT_ADDR           BN0_WF_ARB_TOP_D0SXCR2_ADDR
#define BN0_WF_ARB_TOP_D0SXCR2_D0_SX_SETTLE_CNT_MASK           0x3F000000                // D0_SX_SETTLE_CNT[29..24]
#define BN0_WF_ARB_TOP_D0SXCR2_D0_SX_SETTLE_CNT_SHFT           24
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_SX_CCA_READY_ADDR         BN0_WF_ARB_TOP_D0SXCR2_ADDR
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_SX_CCA_READY_MASK         0x00800000                // D0_WF_SX_CCA_READY[23]
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_SX_CCA_READY_SHFT         23
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_SX_PRE_READY_ADDR         BN0_WF_ARB_TOP_D0SXCR2_ADDR
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_SX_PRE_READY_MASK         0x00400000                // D0_WF_SX_PRE_READY[22]
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_SX_PRE_READY_SHFT         22
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_SX_READY_ADDR             BN0_WF_ARB_TOP_D0SXCR2_ADDR
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_SX_READY_MASK             0x00200000                // D0_WF_SX_READY[21]
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_SX_READY_SHFT             21
#define BN0_WF_ARB_TOP_D0SXCR2_D0_PTA_SX_SEL_SYNC_ADDR         BN0_WF_ARB_TOP_D0SXCR2_ADDR
#define BN0_WF_ARB_TOP_D0SXCR2_D0_PTA_SX_SEL_SYNC_MASK         0x00100000                // D0_PTA_SX_SEL_SYNC[20]
#define BN0_WF_ARB_TOP_D0SXCR2_D0_PTA_SX_SEL_SYNC_SHFT         20
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_TX_ABORT_CNT_ADDR         BN0_WF_ARB_TOP_D0SXCR2_ADDR
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_TX_ABORT_CNT_MASK         0x0000F000                // D0_WF_TX_ABORT_CNT[15..12]
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_TX_ABORT_CNT_SHFT         12
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_REQ_TIME_RST_ADDR         BN0_WF_ARB_TOP_D0SXCR2_ADDR
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_REQ_TIME_RST_MASK         0x00000100                // D0_WF_REQ_TIME_RST[8]
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_REQ_TIME_RST_SHFT         8
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_REQ_TIME_CNT_ADDR         BN0_WF_ARB_TOP_D0SXCR2_ADDR
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_REQ_TIME_CNT_MASK         0x000000FF                // D0_WF_REQ_TIME_CNT[7..0]
#define BN0_WF_ARB_TOP_D0SXCR2_D0_WF_REQ_TIME_CNT_SHFT         0

/* =====================================================================================

  ---D0PB1WERWR (0x820E3000 + 0x258)---

    RESERVED0[15..0]             - (RO) Reserved bits
    BT1WE_EARUP_PERIOD[23..16]   - (RW) BT early update period for WiFi coexistence in 1 wire extend mode. (1us)
                                     For 1 wire mode, this period is for guard time to delay remain window after BTs PTA request deassert. It can set as 0 if this guard time is unnecessary.
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PB1WERWR_BT1WE_EARUP_PERIOD_ADDR      BN0_WF_ARB_TOP_D0PB1WERWR_ADDR
#define BN0_WF_ARB_TOP_D0PB1WERWR_BT1WE_EARUP_PERIOD_MASK      0x00FF0000                // BT1WE_EARUP_PERIOD[23..16]
#define BN0_WF_ARB_TOP_D0PB1WERWR_BT1WE_EARUP_PERIOD_SHFT      16

/* =====================================================================================

  ---D0PTMR0 (0x820E3000 + 0x25C)---

    D0_PTA_GNT_DLY[7..0]         - (RW) This field indicated PTA's grant dealy for WiFi after WiFi assert PTA request.
                                     In unit of T (HW clock).
                                     (Valid only when PTA_INT_TEST_EN=1)
                                     0: delay 0T to assert WiFi grant after request assert
                                     1: delay 1T to assert WiFi grant after request assert
                                     ...
                                     254: delay 254T to assert WiFi grant after request assert
                                     255: always don't assert PTA's grant for WiFi
                                     (for DBDC channel 0)
    D0_WIFI_RXPWR_DIS[8]         - (RW) This field indicated WiFi Rx power disable
                                     (Valid only when D0_PTA_INT_TEST_EN=1)
                                     (for DBDC channel 0)
    RESERVED9[30..9]             - (RO) Reserved bits
    D0_PTA_INT_TEST_EN[31]       - (RW) This field indicated enable PTA internal test mode. It can enable D0PTMR0, D0PTMR6 and give SW an interface to replace PTA system for WiFi.
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR0_D0_PTA_INT_TEST_EN_ADDR         BN0_WF_ARB_TOP_D0PTMR0_ADDR
#define BN0_WF_ARB_TOP_D0PTMR0_D0_PTA_INT_TEST_EN_MASK         0x80000000                // D0_PTA_INT_TEST_EN[31]
#define BN0_WF_ARB_TOP_D0PTMR0_D0_PTA_INT_TEST_EN_SHFT         31
#define BN0_WF_ARB_TOP_D0PTMR0_D0_WIFI_RXPWR_DIS_ADDR          BN0_WF_ARB_TOP_D0PTMR0_ADDR
#define BN0_WF_ARB_TOP_D0PTMR0_D0_WIFI_RXPWR_DIS_MASK          0x00000100                // D0_WIFI_RXPWR_DIS[8]
#define BN0_WF_ARB_TOP_D0PTMR0_D0_WIFI_RXPWR_DIS_SHFT          8
#define BN0_WF_ARB_TOP_D0PTMR0_D0_PTA_GNT_DLY_ADDR             BN0_WF_ARB_TOP_D0PTMR0_ADDR
#define BN0_WF_ARB_TOP_D0PTMR0_D0_PTA_GNT_DLY_MASK             0x000000FF                // D0_PTA_GNT_DLY[7..0]
#define BN0_WF_ARB_TOP_D0PTMR0_D0_PTA_GNT_DLY_SHFT             0

/* =====================================================================================

  ---D0PTMR1 (0x820E3000 + 0x260)---

    D0_WIFI_TX_REQ[0]            - (RO) The WiFi's Tx request to PTA system.
                                     (for DBDC channel 0)
    D0_WIFI_RX_REQ[1]            - (RO) The WiFi's Rx request to PTA system.
                                     (for DBDC channel 0)
    RESERVED2[3..2]              - (RO) Reserved bits
    D0_WIFI_PRI_TAG[7..4]        - (RO) The WiFi's priority tag to PTA system.
                                     (for DBDC channel 0)
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR1_D0_WIFI_PRI_TAG_ADDR            BN0_WF_ARB_TOP_D0PTMR1_ADDR
#define BN0_WF_ARB_TOP_D0PTMR1_D0_WIFI_PRI_TAG_MASK            0x000000F0                // D0_WIFI_PRI_TAG[7..4]
#define BN0_WF_ARB_TOP_D0PTMR1_D0_WIFI_PRI_TAG_SHFT            4
#define BN0_WF_ARB_TOP_D0PTMR1_D0_WIFI_RX_REQ_ADDR             BN0_WF_ARB_TOP_D0PTMR1_ADDR
#define BN0_WF_ARB_TOP_D0PTMR1_D0_WIFI_RX_REQ_MASK             0x00000002                // D0_WIFI_RX_REQ[1]
#define BN0_WF_ARB_TOP_D0PTMR1_D0_WIFI_RX_REQ_SHFT             1
#define BN0_WF_ARB_TOP_D0PTMR1_D0_WIFI_TX_REQ_ADDR             BN0_WF_ARB_TOP_D0PTMR1_ADDR
#define BN0_WF_ARB_TOP_D0PTMR1_D0_WIFI_TX_REQ_MASK             0x00000001                // D0_WIFI_TX_REQ[0]
#define BN0_WF_ARB_TOP_D0PTMR1_D0_WIFI_TX_REQ_SHFT             0

/* =====================================================================================

  ---D0PTMR2 (0x820E3000 + 0x264)---

    D0_OUTBAND_WIN20_BT[14..0]   - (RO) Read only for the WiFi/BT out-band window for primary band in Tx power control mode. This value is set by BT FW in PTASYS, and will be down counting until 0.
                                     In unit of 1us
                                     (for DBDC channel 0)
    RESERVED15[15]               - (RO) Reserved bits
    D0_OUTBAND_WIN40_BT[30..16]  - (RO) Read only for the WiFi/BT out-band window for primary and secondary band in Tx power control mode. This value is set by BT FW in PTASYS, and will be down counting until 0.
                                     In unit of 1us
                                     (for DBDC channel 0)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR2_D0_OUTBAND_WIN40_BT_ADDR        BN0_WF_ARB_TOP_D0PTMR2_ADDR
#define BN0_WF_ARB_TOP_D0PTMR2_D0_OUTBAND_WIN40_BT_MASK        0x7FFF0000                // D0_OUTBAND_WIN40_BT[30..16]
#define BN0_WF_ARB_TOP_D0PTMR2_D0_OUTBAND_WIN40_BT_SHFT        16
#define BN0_WF_ARB_TOP_D0PTMR2_D0_OUTBAND_WIN20_BT_ADDR        BN0_WF_ARB_TOP_D0PTMR2_ADDR
#define BN0_WF_ARB_TOP_D0PTMR2_D0_OUTBAND_WIN20_BT_MASK        0x00007FFF                // D0_OUTBAND_WIN20_BT[14..0]
#define BN0_WF_ARB_TOP_D0PTMR2_D0_OUTBAND_WIN20_BT_SHFT        0

/* =====================================================================================

  ---D0RPTDD4 (0x820E3000 + 0x268)---

    D0_HT_LRATE_DATA_THD0[2..0]  - (RW) This field is used for HT threshold of rate protection for non-no-data packet type with 1 streams. HT rates as following 
                                     (P.S. The HT MCS32 should be compared as HT MCS0)
                                     3'b000: MCS0/MCS32
                                     3'b001: MCS1
                                     3'b010: MCS2
                                     3'b011: MCS3
                                     3'b100: MCS4
                                     3'b101: MCS5
                                     3'b110: MCS6
                                     3'b111: MCS7
                                     (for DBDC channel 0)
    RESERVED3[3]                 - (RO) Reserved bits
    D0_HT_LRATE_DATA_THD1[6..4]  - (RW) This field is used for HT threshold of rate protection for non-no-data packet type with 2 streams. HT rate define as following
                                     3'b000: MCS8
                                     3'b001: MCS9
                                     3'b010: MCS10
                                     3'b011: MCS11
                                     3'b100: MCS12
                                     3'b101: MCS13
                                     3'b110: MCS14
                                     3'b111: MCS15
                                     (for DBDC channel 0)
    RESERVED7[15..7]             - (RO) Reserved bits
    D0_HT_LRATE_RTS_THD0[18..16] - (RW) This field is used for HT threshold of rate protection for RTS packet type with 1 streams. (define same as D0_HT_LRATE_DATA_THD0)
                                     (for DBDC channel 0)
    RESERVED19[19]               - (RO) Reserved bits
    D0_HT_LRATE_RTS_THD1[22..20] - (RW) This field is used for HT threshold of rate protection for RTS packet type with 2 streams. (define same as D0_HT_LRATE_DATA_THD1)
                                     (for DBDC channel 0)
    RESERVED23[31..23]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_RTS_THD1_ADDR      BN0_WF_ARB_TOP_D0RPTDD4_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_RTS_THD1_MASK      0x00700000                // D0_HT_LRATE_RTS_THD1[22..20]
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_RTS_THD1_SHFT      20
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_RTS_THD0_ADDR      BN0_WF_ARB_TOP_D0RPTDD4_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_RTS_THD0_MASK      0x00070000                // D0_HT_LRATE_RTS_THD0[18..16]
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_RTS_THD0_SHFT      16
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_DATA_THD1_ADDR     BN0_WF_ARB_TOP_D0RPTDD4_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_DATA_THD1_MASK     0x00000070                // D0_HT_LRATE_DATA_THD1[6..4]
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_DATA_THD1_SHFT     4
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_DATA_THD0_ADDR     BN0_WF_ARB_TOP_D0RPTDD4_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_DATA_THD0_MASK     0x00000007                // D0_HT_LRATE_DATA_THD0[2..0]
#define BN0_WF_ARB_TOP_D0RPTDD4_D0_HT_LRATE_DATA_THD0_SHFT     0

/* =====================================================================================

  ---D0PTMR4 (0x820E3000 + 0x26C)---

    D0_REMAIN_WIN[14..0]         - (RO) Read only for the final WiFi remaining window after combining BT and LTE remaining window. In unit of 1us
                                     (for DBDC channel 0)
    D0_AGG_TX_END_TOGGLE[15]     - (RO) It will toggle when there was a agg0_tx_end occurs.
                                     (for DBDC channel 0)
    D0_REMAIN_WIN_DBG[30..16]    - (RO) Latch REMAIN_WIN at arb_tx_start. The REMAIN_WIN define as follow.
                                     (for DBDC channel 0)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR4_D0_REMAIN_WIN_DBG_ADDR          BN0_WF_ARB_TOP_D0PTMR4_ADDR
#define BN0_WF_ARB_TOP_D0PTMR4_D0_REMAIN_WIN_DBG_MASK          0x7FFF0000                // D0_REMAIN_WIN_DBG[30..16]
#define BN0_WF_ARB_TOP_D0PTMR4_D0_REMAIN_WIN_DBG_SHFT          16
#define BN0_WF_ARB_TOP_D0PTMR4_D0_AGG_TX_END_TOGGLE_ADDR       BN0_WF_ARB_TOP_D0PTMR4_ADDR
#define BN0_WF_ARB_TOP_D0PTMR4_D0_AGG_TX_END_TOGGLE_MASK       0x00008000                // D0_AGG_TX_END_TOGGLE[15]
#define BN0_WF_ARB_TOP_D0PTMR4_D0_AGG_TX_END_TOGGLE_SHFT       15
#define BN0_WF_ARB_TOP_D0PTMR4_D0_REMAIN_WIN_ADDR              BN0_WF_ARB_TOP_D0PTMR4_ADDR
#define BN0_WF_ARB_TOP_D0PTMR4_D0_REMAIN_WIN_MASK              0x00007FFF                // D0_REMAIN_WIN[14..0]
#define BN0_WF_ARB_TOP_D0PTMR4_D0_REMAIN_WIN_SHFT              0

/* =====================================================================================

  ---D0PTMR5 (0x820E3000 + 0x270)---

    D0_SW_WIFI_TX_REQ[0]         - (RW) This field indicates WiFi Tx request to PTASYS.
                                     (Valid only when D0_PTA_EXT_TEST_EN=1)
                                     (for DBDC channel 0)
    D0_SW_WIFI_RX_REQ[1]         - (RW) This field indicates WiFi Rx request to PTASYS.
                                     (Valid only when D0_PTA_EXT_TEST_EN=1)
                                     (for DBDC channel 0)
    RESERVED2[3..2]              - (RO) Reserved bits
    D0_SW_WIFI_PRI_TAG[7..4]     - (RW) This field indicates WiFi's priority tag to PTASYS.
                                     (Valid only when D0_PTA_EXT_TEST_EN=1)
                                     (for DBDC channel 0)
    D0_PTA_GRANT[8]              - (RO) This field indicates PTA master's output wifi_grant
                                     (for DBDC channel 0)
    D0_PTA_RXPWR_DIS[9]          - (RO) This field indicates PTA master's output wifi_rxpwr_dis
                                     (for DBDC channel 0)
    RESERVED10[15..10]           - (RO) Reserved bits
    D0_BT_RW_SRC_SEL[17..16]     - (RW) (Valid only when PTA_INT_TEST_EN=1)
                                     This field indicated BT Remaining Window source
                                      0: Remaining Window from ESI mode (bt_rw_up, bt_rw_intvl, bt_rw_ow_cnt and bt_rw_ow_cmpnst)
                                      1: Remaining Window from 1 wire extend mode (bt_rsvd_start, bt_rsvd_end, bt_pp_wp)
                                      2: Remaining Window from 1 wire mode (bt_rsvd_end, bt_pp_wp, bt_ext_period)
    RESERVED18[29..18]           - (RO) Reserved bits
    D0_PTA5_EN[30]               - (RW) This field indicates support PTA5 interface or not.
                                     0: only support PTA version < 5, but don't support PTA version >= 5. The priority tag change by PTA request re-assert
                                     1: only support PTA version >= 5, but don't support PTA version < 5. The priority tag changer by extra IO. Hence, PTA request will keep assert
                                     (for DBDC channel 1)
    D0_PTA_EXT_TEST_EN[31]       - (RW) This field indicates enable PTA external test mode. It can enable D0PTMR5 and give SW an interface to replace WiFi system for PTA.
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA_EXT_TEST_EN_ADDR         BN0_WF_ARB_TOP_D0PTMR5_ADDR
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA_EXT_TEST_EN_MASK         0x80000000                // D0_PTA_EXT_TEST_EN[31]
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA_EXT_TEST_EN_SHFT         31
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA5_EN_ADDR                 BN0_WF_ARB_TOP_D0PTMR5_ADDR
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA5_EN_MASK                 0x40000000                // D0_PTA5_EN[30]
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA5_EN_SHFT                 30
#define BN0_WF_ARB_TOP_D0PTMR5_D0_BT_RW_SRC_SEL_ADDR           BN0_WF_ARB_TOP_D0PTMR5_ADDR
#define BN0_WF_ARB_TOP_D0PTMR5_D0_BT_RW_SRC_SEL_MASK           0x00030000                // D0_BT_RW_SRC_SEL[17..16]
#define BN0_WF_ARB_TOP_D0PTMR5_D0_BT_RW_SRC_SEL_SHFT           16
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA_RXPWR_DIS_ADDR           BN0_WF_ARB_TOP_D0PTMR5_ADDR
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA_RXPWR_DIS_MASK           0x00000200                // D0_PTA_RXPWR_DIS[9]
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA_RXPWR_DIS_SHFT           9
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA_GRANT_ADDR               BN0_WF_ARB_TOP_D0PTMR5_ADDR
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA_GRANT_MASK               0x00000100                // D0_PTA_GRANT[8]
#define BN0_WF_ARB_TOP_D0PTMR5_D0_PTA_GRANT_SHFT               8
#define BN0_WF_ARB_TOP_D0PTMR5_D0_SW_WIFI_PRI_TAG_ADDR         BN0_WF_ARB_TOP_D0PTMR5_ADDR
#define BN0_WF_ARB_TOP_D0PTMR5_D0_SW_WIFI_PRI_TAG_MASK         0x000000F0                // D0_SW_WIFI_PRI_TAG[7..4]
#define BN0_WF_ARB_TOP_D0PTMR5_D0_SW_WIFI_PRI_TAG_SHFT         4
#define BN0_WF_ARB_TOP_D0PTMR5_D0_SW_WIFI_RX_REQ_ADDR          BN0_WF_ARB_TOP_D0PTMR5_ADDR
#define BN0_WF_ARB_TOP_D0PTMR5_D0_SW_WIFI_RX_REQ_MASK          0x00000002                // D0_SW_WIFI_RX_REQ[1]
#define BN0_WF_ARB_TOP_D0PTMR5_D0_SW_WIFI_RX_REQ_SHFT          1
#define BN0_WF_ARB_TOP_D0PTMR5_D0_SW_WIFI_TX_REQ_ADDR          BN0_WF_ARB_TOP_D0PTMR5_ADDR
#define BN0_WF_ARB_TOP_D0PTMR5_D0_SW_WIFI_TX_REQ_MASK          0x00000001                // D0_SW_WIFI_TX_REQ[0]
#define BN0_WF_ARB_TOP_D0PTMR5_D0_SW_WIFI_TX_REQ_SHFT          0

/* =====================================================================================

  ---D0RPTDD5 (0x820E3000 + 0x274)---

    D0_VHT_LRATE_DATA_THD0[3..0] - (RW) This field is used for VHT threshold of rate protection for non-no-data packet type with 1 streams. VHT rates as following 
                                     4'b0000: MCS0
                                     4'b0001: MCS1
                                     4'b0010: MCS2
                                     4'b0011: MCS3
                                     4'b0100: MCS4
                                     4'b0101: MCS5
                                     4'b0110: MCS6
                                     4'b0111: MCS7
                                     4'b1000: MCS8
                                     4'b1001: MCS9
                                     (for DBDC channel 0)
    D0_VHT_LRATE_DATA_THD1[7..4] - (RW) This field is used for VHT threshold of rate protection for non-no-data packet type with 2 streams. (define same as D0_VHT_LRATE_DATA_THD0)
                                     (for DBDC channel 0)
    RESERVED8[15..8]             - (RO) Reserved bits
    D0_VHT_LRATE_RTS_THD0[19..16] - (RW) This field is used for VHT threshold of rate protection for RTS packet type with 1 streams. (define same as D0_VHT_LRATE_DATA_THD0)
                                     (for DBDC channel 0)
    D0_VHT_LRATE_RTS_THD1[23..20] - (RW) This field is used for VHT threshold of rate protection for RTS packet type with 2 streams. (define same as D0_VHT_LRATE_DATA_THD1)
                                     (for DBDC channel 0)
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_RTS_THD1_ADDR     BN0_WF_ARB_TOP_D0RPTDD5_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_RTS_THD1_MASK     0x00F00000                // D0_VHT_LRATE_RTS_THD1[23..20]
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_RTS_THD1_SHFT     20
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_RTS_THD0_ADDR     BN0_WF_ARB_TOP_D0RPTDD5_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_RTS_THD0_MASK     0x000F0000                // D0_VHT_LRATE_RTS_THD0[19..16]
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_RTS_THD0_SHFT     16
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_DATA_THD1_ADDR    BN0_WF_ARB_TOP_D0RPTDD5_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_DATA_THD1_MASK    0x000000F0                // D0_VHT_LRATE_DATA_THD1[7..4]
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_DATA_THD1_SHFT    4
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_DATA_THD0_ADDR    BN0_WF_ARB_TOP_D0RPTDD5_ADDR
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_DATA_THD0_MASK    0x0000000F                // D0_VHT_LRATE_DATA_THD0[3..0]
#define BN0_WF_ARB_TOP_D0RPTDD5_D0_VHT_LRATE_DATA_THD0_SHFT    0

/* =====================================================================================

  ---D0PTMR7 (0x820E3000 + 0x278)---

    D0_BT_RW_OW_CNT[10..0]       - (RW) This field provide smaller unit for D0_BT_RW_INTVL, D0_BT_OW_INTVL20, and D0_BT_OW_INTVL.  
                                      If D0_BT_RW_OB_MODE=0, all 11 bits are valid which unit is 1us.
                                      If D0_BT_RW_OB_MODE=1, only bit 5 to bit 10 are valid bits, the range is from 1 to 40. Other bits should write 0, which means the unit of this value is 32 us.(D0_BT_RW_OW_CNT, D0_BT_OW_INTVL20, D0_BT_OW_INTVL40 and D0_BT_RW_INTVL must update at the same time)
                                     (Valid only when D0_PTA_INT_TEST_EN=1)
                                     (for DBDC channel 0)
    RESERVED11[23..11]           - (RO) Reserved bits
    D0_BT_RW_INTVL[31..24]       - (RW) This field indicates WiFi Tx remaining window.
                                     In unit of 625us
                                     (D0_BT_RW_OW_CNTand D0_BT_RW_INTVL must update at the same time)
                                     (Valid only when D0_PTA_INT_TEST_EN=1)
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR7_D0_BT_RW_INTVL_ADDR             BN0_WF_ARB_TOP_D0PTMR7_ADDR
#define BN0_WF_ARB_TOP_D0PTMR7_D0_BT_RW_INTVL_MASK             0xFF000000                // D0_BT_RW_INTVL[31..24]
#define BN0_WF_ARB_TOP_D0PTMR7_D0_BT_RW_INTVL_SHFT             24
#define BN0_WF_ARB_TOP_D0PTMR7_D0_BT_RW_OW_CNT_ADDR            BN0_WF_ARB_TOP_D0PTMR7_ADDR
#define BN0_WF_ARB_TOP_D0PTMR7_D0_BT_RW_OW_CNT_MASK            0x000007FF                // D0_BT_RW_OW_CNT[10..0]
#define BN0_WF_ARB_TOP_D0PTMR7_D0_BT_RW_OW_CNT_SHFT            0

/* =====================================================================================

  ---D0PTMR8 (0x820E3000 + 0x27C)---

    D0_BT_PP_WP[8..0]            - (RW) (Valid only when PTA_INT_TEST_EN=1)
                                     The BT 1 wire extend mode periodic period or WiFi period from PTA system.
                                     Unit is 48 us
    RESERVED9[10..9]             - (RO) Reserved bits
    D0_BT_RSVD_START_HONOR[11]   - (RW) (Valid only when PTA_INT_TEST_EN=1)
                                     The BT 1 wire extend mode reserved start honor from PTA system.
                                     It only valid when BT_RSVD_END assert.
                                     When this bit assert, the remain_win release is depend on pervious BT_RSVD_START or not to determine information is from BT_RSVD_STAR or BT_RSVD_END
                                     When this bit deassert, the remain_win release is always from BT_RSVD_END
    D0_BT_RSVD_END[12]           - (W1S) (Valid only when PTA_INT_TEST_EN=1)
                                     The BT 1 wire extend mode reserved start from PTA system.
                                     HW only trigger 1 pulse like PTA input. Hence, this bit always read as 0.
                                     When BT_RSVD_EDN assert, 
                                     if has previous BT_RSVD_START and BT_RSVD_START_HONOR, HW will release remain_win that get from BT_RSVD_START.
                                     Else, HW will release remain_win that get from BT_RSVD_END
    D0_BT_RSVD_START[13]         - (W1S) (Valid only when PTA_INT_TEST_EN=1)
                                     The BT 1 wire extend mode reserved start from PTA system.
                                     HW only trigger 1 pulse like PTA input. Hence, this bit always read as 0.
                                     When BT_RSVD_START assert, HW will start BT_CURR_TIME and wait BT_RSVD_END.
    D0_BT_EXT_PERIOD[15..14]     - (RW) (Valid only when PTA_INT_TEST_EN=1)
                                     The BT 1 wire mode extra period from PTA system.
                                     When BT_RSVD_END assert, BT_PP_WP indicate remaining window release, besides the 1 wire mode has extra remaining window release.
                                      0: extra remaining window 489us (625 - 136) 
                                      1: extra remaining window 249us (625 - 376)
                                      2: extra remaining window 223us (625 - 402)
                                      3: extra remaining window 0us (625 - 625)
    D0_BT_CURR_TIME[30..16]      - (RO) The field indicates current time in this BT RSVD preiod.
                                     When PTA_INT_TEST_EN = 0, this field is read only.
                                     When PTA_INT_TEST_EN = 1, this field can program for test
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_CURR_TIME_ADDR            BN0_WF_ARB_TOP_D0PTMR8_ADDR
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_CURR_TIME_MASK            0x7FFF0000                // D0_BT_CURR_TIME[30..16]
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_CURR_TIME_SHFT            16
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_EXT_PERIOD_ADDR           BN0_WF_ARB_TOP_D0PTMR8_ADDR
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_EXT_PERIOD_MASK           0x0000C000                // D0_BT_EXT_PERIOD[15..14]
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_EXT_PERIOD_SHFT           14
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_RSVD_START_ADDR           BN0_WF_ARB_TOP_D0PTMR8_ADDR
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_RSVD_START_MASK           0x00002000                // D0_BT_RSVD_START[13]
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_RSVD_START_SHFT           13
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_RSVD_END_ADDR             BN0_WF_ARB_TOP_D0PTMR8_ADDR
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_RSVD_END_MASK             0x00001000                // D0_BT_RSVD_END[12]
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_RSVD_END_SHFT             12
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_RSVD_START_HONOR_ADDR     BN0_WF_ARB_TOP_D0PTMR8_ADDR
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_RSVD_START_HONOR_MASK     0x00000800                // D0_BT_RSVD_START_HONOR[11]
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_RSVD_START_HONOR_SHFT     11
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_PP_WP_ADDR                BN0_WF_ARB_TOP_D0PTMR8_ADDR
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_PP_WP_MASK                0x000001FF                // D0_BT_PP_WP[8..0]
#define BN0_WF_ARB_TOP_D0PTMR8_D0_BT_PP_WP_SHFT                0

/* =====================================================================================

  ---D0PTMR9 (0x820E3000 + 0x280)---

    D0_LTE_REMAIN_WIN[14..0]     - (RW) This field provides the remaining window from LTE.
                                     The unit is 1us.
                                     (Valid only when D0_PTA_INT_TEST_EN=1)
                                     (for DBDC channel 0)
    RESERVED15[15]               - (RO) Reserved bits
    D0_LTE_REMAIN_WIN_REAL[30..16] - (RO) The read value is the remaining window from LTE (either from PTASYS or test mode).
                                     The unit is 1us.
                                     (for DBDC channel 0)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR9_D0_LTE_REMAIN_WIN_REAL_ADDR     BN0_WF_ARB_TOP_D0PTMR9_ADDR
#define BN0_WF_ARB_TOP_D0PTMR9_D0_LTE_REMAIN_WIN_REAL_MASK     0x7FFF0000                // D0_LTE_REMAIN_WIN_REAL[30..16]
#define BN0_WF_ARB_TOP_D0PTMR9_D0_LTE_REMAIN_WIN_REAL_SHFT     16
#define BN0_WF_ARB_TOP_D0PTMR9_D0_LTE_REMAIN_WIN_ADDR          BN0_WF_ARB_TOP_D0PTMR9_ADDR
#define BN0_WF_ARB_TOP_D0PTMR9_D0_LTE_REMAIN_WIN_MASK          0x00007FFF                // D0_LTE_REMAIN_WIN[14..0]
#define BN0_WF_ARB_TOP_D0PTMR9_D0_LTE_REMAIN_WIN_SHFT          0

/* =====================================================================================

  ---D0PTMR10 (0x820E3000 + 0x284)---

    D0_BT_REMAIN_WIN_REAL[17..0] - (RO) The read value is the remaining window from BT (either from PTASYS or test mode).
                                     The unit is 1us.
                                     (for DBDC channel 0)
    RESERVED18[31..18]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR10_D0_BT_REMAIN_WIN_REAL_ADDR     BN0_WF_ARB_TOP_D0PTMR10_ADDR
#define BN0_WF_ARB_TOP_D0PTMR10_D0_BT_REMAIN_WIN_REAL_MASK     0x0003FFFF                // D0_BT_REMAIN_WIN_REAL[17..0]
#define BN0_WF_ARB_TOP_D0PTMR10_D0_BT_REMAIN_WIN_REAL_SHFT     0

/* =====================================================================================

  ---D0PTMR11 (0x820E3000 + 0x288)---

    D0_BT_RW_OW_CNT_FDD[10..0]   - (RW) This field provide smaller unit for D0_BT_RW_INTVL, D0_BT_OW_INTVL20, and D0_BT_OW_INTVL.  
                                      If D0_BT_RW_OB_MODE=0, all 11 bits are valid which unit is 1us.
                                      If D0_BT_RW_OB_MODE=1, only bit 5 to bit 10 are valid bits, the range is from 1 to 40. Other bits should write 0, which means the unit of this value is 32 us.(D0_BT_RW_OW_CNT, D0_BT_OW_INTVL20, D0_BT_OW_INTVL40 and D0_BT_RW_INTVL must update at the same time)
                                     (Valid only when D0_PTA_INT_TEST_EN=1)
                                     (for DBDC channel 0)
    RESERVED11[23..11]           - (RO) Reserved bits
    D0_BT_RW_INTVL_FDD[31..24]   - (RW) This field indicates WiFi Tx remaining window.
                                     In unit of 625us
                                     (D0_BT_RW_OW_CNTand D0_BT_RW_INTVL must update at the same time)
                                     (Valid only when D0_PTA_INT_TEST_EN=1)
                                     (for DBDC channel 0)

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR11_D0_BT_RW_INTVL_FDD_ADDR        BN0_WF_ARB_TOP_D0PTMR11_ADDR
#define BN0_WF_ARB_TOP_D0PTMR11_D0_BT_RW_INTVL_FDD_MASK        0xFF000000                // D0_BT_RW_INTVL_FDD[31..24]
#define BN0_WF_ARB_TOP_D0PTMR11_D0_BT_RW_INTVL_FDD_SHFT        24
#define BN0_WF_ARB_TOP_D0PTMR11_D0_BT_RW_OW_CNT_FDD_ADDR       BN0_WF_ARB_TOP_D0PTMR11_ADDR
#define BN0_WF_ARB_TOP_D0PTMR11_D0_BT_RW_OW_CNT_FDD_MASK       0x000007FF                // D0_BT_RW_OW_CNT_FDD[10..0]
#define BN0_WF_ARB_TOP_D0PTMR11_D0_BT_RW_OW_CNT_FDD_SHFT       0

/* =====================================================================================

  ---D0PTMR12 (0x820E3000 + 0x28C)---

    D0_REMAIN_WIN_REAL_FDD_TMP1[17..0] - (RO) D0_REMAIN_WIN_REAL_FDD_TMP1
    RESERVED18[31..18]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_ARB_TOP_D0PTMR12_D0_REMAIN_WIN_REAL_FDD_TMP1_ADDR BN0_WF_ARB_TOP_D0PTMR12_ADDR
#define BN0_WF_ARB_TOP_D0PTMR12_D0_REMAIN_WIN_REAL_FDD_TMP1_MASK 0x0003FFFF                // D0_REMAIN_WIN_REAL_FDD_TMP1[17..0]
#define BN0_WF_ARB_TOP_D0PTMR12_D0_REMAIN_WIN_REAL_FDD_TMP1_SHFT 0

#ifdef __cplusplus
}
#endif

#endif // __BN0_WF_ARB_TOP_REGS_H__
